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[ASAHI KASEI]
AK8855
AK8855
NTSC/PAL Digital Video Decoder
General Description
The AK8855 decodes the NTSC, PAL Composite Video signal into Digital code. Outputs are ITU-R BT. 601 Level compatible Y, Cb and Cr signals. Decoded results are scaled to QVGA/CIF sizes etc.. Output interface is camera-interface in ITU-R BT.656-alike output format. When such information as Closed Caption, VBID, WSS are encoded on the Video signal, each code can be read out externally. When the Macrovision signal is super-imposed, its information can also externally be read out.
Features * * * * * * * * * * * * * * *
NTSC-M / PAL- B, D, G, H, I Composite signal decoding process 2-CH input acceptable (selector is integrated on-chip ) On-chip 10 Bit ADC (operation at 24.5454 MHz or 27 MHz ) Fixed clock Sampling On-chip PLL ( 27 MHz clock generation from 24.5454 MHz ) On-chip Quartz Crystal Oscillator circuit Pixel Position Correction function Selectable Picture sizes (QVGA / VGA / QCIF / CIF / 601 ) - Rotated Picture Mode output available (ex. QVGA : 240 X 180 ) Selectable Output rate (525 : 30 / 15 / 7.5 625 : 25 / 12.5 / 6.25 [ frames / sec ] ) On-chip Anti-Aliasing Filter On-chip PGA ( 0 dB ~ 12 dB ) Auto Color Control (ACC) function Adaptive Auto Gain Control (AGC) function Primary YC Separation Output Interface - ITU-R BT.656-alike output format (4:2:2 8 Bit parallel output with EAV / SAV ) * * depending on the input signal quality, ITU-R BT. 656 compatible output may not be available. - Camera Interface - Interface by HD / VD / DVALID signals Closed Caption decoding function ( to be output by register setting ) VBID ( CGMS-A ) decoding function ( CRCC decode ) ( to be output by register setting ) WSS decoding function ( to be output by register setting ) Macrovision signal detect function Power-down function I2C Control compatible Internal operating power supply 2.7 V ~ 3.3 V supplying I / F Power Supply ( 1.6 V ~ 2.0 V or 2.7 V ~ 3.3 V ) Package 57 FBGA
* * * * * * * * *
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AK8855
Total Functional Block Diagram
XTO XTI SDA SCL RSTN OE
24.5454MHz CLKMOD PLL 24.5454/27.00MHz
Microprocessor I/F Register
CLKO CLK Y 1D Y/C Separation C Y Output Ctrl Down Cb Sampler Cr Y Cb Pixel Interpolator Cr Output I/F
AIN1 AIN2
Selector
PGA
ADC
Chrominance Decode
U V
D[7:0]
CLAMP
AAF
* Sync-Separation * AGC Info. * VBID
HD VD DVALID
ATIO TEST2
HD/HV VD/VAF DVALID FIELD NSIG
ANALOG BLOCK
VREF
DIGITAL BLOCK TEST0 TEST1 PDN DVDD DVSS PVDD PVSS
AVDD AVSS VRP VCOM VRN IREF
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AK8855
Ordering Guide
AK8855VG 57 pin FBGA
Pin Layout Drawing
9 8 7 6 5 4 3 2 1 A B C D E F G H J Bottom View
A B C D E F G H J
1 NC VCOM AIN1 AVDD AIN2 TEST0 SCL SDA NC
2 VRN IREF AVSS BVSS DVSS DVDD TEST1 PDN OE
3 VRP TEST2 NC
4 ATIO BVSS
5 XTI CLKMO D
6 XTO DVSS
7 DVDD BVSS
8 FIELD NSIG HD PVSS D1 DVSS BVSS CLKO PVSS
9 NC DVALID VD PVDD D0 DVDD D2 D3 NC
RSTN PVDD
PVSS DVDD
DVSS D7
D5 D6
D4 PVDD
TOP View
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AK8855
Pin Functional Description
Pin# A5 Pin Name XTI I/O I Functional Outline Quartz crystal resonator connecting pin ( to be grounded to Digital ground via a 18 pF capacitor in the recommended circuit ). - 24.5454 MHz crystal resonator should be used. - input from 24.5454 MHz crystal oscillator is connected to this pin. Quartz crystal resonator connecting pin ( to be grounded to Digital ground via a 22 pF capacitor in the recommended circuit ). - 24.5454 MHz crystal resonator should be used. - This pin outputs DVSS level at PDN = L. - when a crystal resonator is not used, this pin is left open ( NC ) or connected to DVSS. Clock mode setting pin. Connect to either DVDD or DVSS. DVSS grounding : crystal resonator is used DVDD connection : crystal oscillator is used Output enable pin L : output pins are put into Hi-Z condition H : data is output I2C data pin This pin is pulled-up to PVDD. I2C clock input pin Input level of lower-than-PVDD should be input. Reset signal input pin L : reset H : normal operation Output pin conditions are in Hi-Z when RSTN pin is at low. power-down control pin L : power-down H : normal operation Data clock output pin for output I/ F Data output pin Video decode data is output ( MSB ) ( note ) Data output pin ( note ) Data output pin ( note ) Data output pin ( note ) Data output pin ( note ) Data output pin ( note ) Data output pin ( note ) Data output pin ( LSB ) ( note ) HD / HV timing signal output pin ( note ) VD / VAF timing signal output pin ( pin ) pin to indicate a valid Video interval ( note ) FIELD signal output pin ( note ) to show a status at no signal input condition ( note ) L : with input signal H : no signal input
A6
XTO
O
B5
CLKMOD
I
J2 H1 G1
OE SDA SCL
I I/O I
H3
RSTN
I
H2 H8 J5 J6 H6 H7 H9 G9 E8 E9 C8 C9 B9 A8 B8
PDN CLKO D7 D6 D5 D4 D3 D2 D1 D0 HD/HV VD/VAF DVALID FIELD NSIG
I O O O O O O O O O O O O O O
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[ASAHI KASEI] C1 E1 B2 AIN1 AIN2 IREF I I O Analog input pin ( 1 ) Analog input pin ( 2 )
AK8855
A2
VRN
O
A3
VRP
O
B1
VCOM
O
Reference current setting pin Connect this pin to Analog ground via a 4.7 kohm ( <= 1 % accuracy ) resistor. This pin becomes Hi-Z output at power-down mode. internal negative reference voltage for AD converter - connect this pin to Analog ground via a 0.1 uF or larger capacitor. - there is a case when this pin becomes Hi-Z output at power-down. - Do not use this as a reference voltage source for external circuit(s). O internal positive reference voltage for AD converter - connect this pin to Analog ground via a 0.1 uF or larger capacitor. - there is a case when this pin becomes Hi-Z output at power-down. - do not use this as a reference voltage source for external circuit(s). internal common voltage for AD converter - connect this pin to Analog ground via a 0.1 uF or larger capacitor. - there is a case when this pin becomes Hi-Z output at power-down. - do not use this as a reference voltage source for external circuit(s). ground pin for crystal oscillator circuit power supply pin for crystal oscillator circuit Analog power supply pin Analog ground pin Digital power supply pins Digital ground pins Substrate ground pins Connect those pins to Analog ground. power supply pins for interface Interface power supply for CLKO, OE, PDN, RSTN, D [7:0], FIELD, HD, VD, NSIG, DVALID, SDA, SCL Ground pins for interface power supply Analog test pin Connect this pin to AVDD for normal operation Test mode setting pin. Connect this pin to DVSS Test mode setting pin. Connect this pin to DVSS connect this pin to AVSS NC pin to be connected to AVSS pin to be connected to AVSS ( index pin ) pin to be connected to DVSS pin to be connected to DVSS pin to be connected to DVSS
B6 A7 D1 C2 F2, J4, F9 E2, H5, F8 D2, G8, B7, B4 J3, J7, D9 H4, D8, J8 A4 F1 G2 B3 A1 C3 J1 J9 A9
DVSS DVDD AVDD AVSS DVDD DVSS BVSS
G P P G P G G
PVDD PVSS ATIO TEST0 TEST1 TEST2 NC NC NC NC NC
P G I I/O I/O O NC NC NC NC NC
I : input pin O : output pin I/O : input / output pin P : power supply pin G : ground pin note ) the AK8855 starts to output after it is reset. When no signal is input, Black level data ( Y = 0x10, Cb/Cr = 0x80 ) is output.
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AK8855
Electrical Characteristics
(1) Absolute Maximum Ratings Parameter Supply voltage DVDD, AVDD, PVDD Analog Input pin voltage (VinA) Clock input voltage (Vckin) Digital Input pin voltage (VinD) Min -0.3 -0.3 -0.3 -0.3 Max 4.5 AVDD + 0.3 DVDD + 0.3 PVDD + 0.3 Units V V V V AIN1, AIN2 XTI OE, PDN,RSTN, SDA, SCL Note
-10 10 mA Input pin current (Iin) -40 125 Storage temperature C Power supply voltages are values where each ground pin ( DVSS = AVSS = PVSS ) is at 0 V ( voltage reference ).All power supply ground pins DVSS, AVSS and PVSS should be at same potential. When to connect to Data bus such digital output pins as CLKO, D[7:0], FIELD, HD, VD, NSIG, DVALID, Data bus operating voltage must be within the input pin voltage range as described above. (2) Recommended Operating Conditions Parameter Min Typ. Max Units Conditions Supply voltage * 3.0 3.3 V AVDD = DVDD 2.7 AVDD,DVDD 1.6 1.8 2.0 V interface power supply 2.7 3.0 3.3 V PVDD = DVDD PVDD Operating temperature 85 -30 C (Ta) * power supply voltages are values where each ground pin ( PVSS = AVSS = PVSS ) is at 0 V ( voltage reference ).All power supply ground pins DVSS, AVSS and PVSS should be at same potential. (3) DC Characteristics < operating voltage : DVDD 2.7V~3.3V / PVDD 2.7V~3.3V / PVDD 1.6 V~2.0 V , temperature -30~+85C > Parameter Symbol Min Typ Max Units Conditions
Digital input H voltage (VIH) VIH1 VIH2 VIH3 VIL1 VIL2 VIL3 IL VOH1 VOH2 VOL1 VOL2 0.7PVDD 0.8PVDD 0.7DVDD 0.3PVDD 0.2PVDD 0.3DVDD +/-10 2.2 1.3 0.4 0.4 V V V V uA V V V V IOH =-1mA PVDD = 2.7~3.3V IOH =-600uA PVDD = 1.6~2.0V IOL = 2mA PVDD = 2.7~3.3V IOL = 1mA PVDD =1.6~2.0V IOLC = 3mA PVDD = 2.7~3.3V PVDD =1.6~2.0V PVDD = 2.7~3.3V PVDD =1.6~2.0V
Digital input L voltage (VIL) Digital input leak current Digital (VOH) output H voltage
Digital output L voltage (VOL)
VOLC 0.4 V I2C (SDA) L output note ) Digital output pins refer to CLKO, D[7:0], FIELD, HD/HV, VD/VAF, NSIG and DVALID pin outputs in general term. Digital inputs which are specified by VIH1, VIH2, VIL1 and VIL2 refer to OE, PDN, RSTN,SCL and SDA pin inputs in general term. Digital input which is specified by VIH3 and VIL3 means XTI input. SDA pin output is not included in digital output pin unless otherwise noted.
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[ASAHI KASEI] (4) AC Characteristics Parameter
Digital output maximum allowable load capacitance
AK8855 Symbol
CL
Min
Typ
Max
15 30
Units
pF pF
Conditions
PVDD =1.6~2.0V PVDD = 2.7~3.3V
(5) Analog Characteristics < AVDD = 3.0 V, temperature 25 C > Selector Clamp Parameter Symbol Min Typ
Maximum input range Clamp level Clamp current VIMX VYCP CLPI 0.9 150
Max
1
Units
VPP V uA
Conditions
PGA Parameter
Resolution Minimum gain Maximum gain Gain step
Symbol
GMN GMX GST
Min
Typ
7 0 12 0.094
Max
Units
bit dB dB dB
Conditions
AD Converter Parameter
Resolution operating clock frequency Integral non-linearity error Differential non-linearity error S/N S/(N+D) ADC internal common voltage ADC ADC internal positive-side VREF voltage ADC internal negative-side VREF voltage
Symbol
RES FS INL DNL SN SND VCOM VRP VRN
Min
Typ
10 24.5454 27 2.0 1.0 54 51 1.3 1.7 0.9
Max
Units
bits MHz
Conditions
4.0 2.0
LSB LSB dB dB V V V
fs = 27MHz fs = 27MHz fin = 1MHz Ain = -1dB fs = 27MHz fin = 1MHz Ain = -1dB fs = 27MHz
(6) Current consumption < DVDD = AVDD = PVDD = 3.0 V, Ta = -30 ~ +85C > Symb Parameter Min Typ Max Units ol
Operating power supply current Total Analog part power supply ( AVDD ) Digital part power supply ( DVDD) Idda Iddd 66 24 28 (30) Interface part power supply ( PVDD ) Power-down current Total power-down current Analog part power supply ( AVDD ) Digital part power supply ( DVDD ) Interface part power supply ( PVDD ) Iddp 14 1 1 1 1 100 86 mA mA mA mA mA uA uA uA uA
Conditions
note1) When an external clock source is input When an external clock source is input (when a crystal resonator is connected) CL = 30pF
note2),note3)
note 1 ) when to decode color bar signal during 601 output mode ( internal system clock at 27 MHz operation ). note 2 ) output bus potential of data output pin is fixed at PVDD when to measure power-down current. Input level of digital input pins ( PDN, RSTN, OE ) and input level of I2C pins ( SCLK, SDA ) are fixed to either PVSS or PVDD. note 3 ) set digital output pins to PVDD potential, or set OE pin high in power-down setting mode.
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[ASAHI KASEI] (7) Quartz Crystal Oscillator circuit Quartz crystal resonator and externally connecting load capacitance Parameter Symbol Min Typ Max Oscillating frequency f0 24.5454 Frequency accuracy delta f / f +/-100 load capacitance CL 15 effective equivalent resistance Re 100 Parallel capacitance C0 0.85 XTI pin externally connecting load CXI 18 capacitance XTLO pin externally connecting CXO 22 load capacitance note 1 ) effective equivalent resistance is generally given as : Re = R1 x ( 1 + CO / CL ) square Where R1 : serial equivalent resistance of crystal resonator CO : parallel capacitance of crystal resonator Circuit connection example
gm
AK8855 Units [MHz] [ppm] [pF] [] [pF] Conditions
note1)
[pF] [pF]
Rf
AK8855
XTI
XTO Rd
Externally connecting circuit
CXI =18pF
CXO =22pF
Note ) Rd : as for the necessity of limiting resistor and its value, refer to the quartz crystal resonator specification which is to be used.
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AK8855
AC Timing
( DVDD 2.7 V ~ 3.3 V / PVDD 1.6 V ~ 2.0 V or PVDD 2.7 V ~ 3.3 V, Ta at -30 ~ +85 C ) loading condition : CL = 30 pF ( at 3.0 V I / F ) CL = 15 pF ( at 1.8 V I / F ) (1) Clock Input ( XTI input )
fC L K tC L K L tC L K H V IH 3 1 /2 L e ve l o f V IH 3 a n d V IL 3 V IL 3
Parameter CLK CLK duty ratio Frequency stability
Symbol fCLK pCLKD
Min. 40
Typ. 24.5454
Max 60 +/-100
Unit MHz % ppm
(2) CLKO Output
fC L K O
1 /2 D V D D
Parameter
Symbol
Min.
Typ. 6.75 12.2727
Max
Unit
CLKO
fCLKO
13.5 24.5454 27
MHz
Conditions QCIF QVGA / Rotated QVGA / Rotated CIF CIF(PAL) VGA CIF(NTSC)/601
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[ASAHI KASEI] (3) Output Data Timing (3-1) All digital output signals except for NSIG output ( VGA / 601 / CIF ( NTSC ))
CLKINV-bit = 0 ( by register setting )
CLKO tODL1 tOHD1 Output signal 1/2PVDD
AK8855
0.7PVDD 0.3PVDD
CLKINV-bit = High ( by register setting )
CLKO tODL1 tOHD1 Output signal 07PVDD 0.3PVDD 1/2PVDD
Parameter Output Data Delay Time Output Data Hold Time
Symbol tODL1 tOHD1
Min.
Typ.
Max 28
Unit nsec
Conditions
3
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[ASAHI KASEI] AK8855 (3-2) All output signals except for NSIG output ( QVGA / QCIF / CIF ( PAL ) / Rotated QVGA / Rotated CIF )
CLKINV-bit = 0 ( by register setting )
CLKO tDS tDH 1/2PVDD
Output signal
0.7PVDD 0.3PVDD
CLKINV-bit = 1 ( by register setting )
CLKO tDS tDH 1/2PVDD
Output signal
0.7PVDD 0.3PVDD
Parameter Output Data Setup Time Output Data Hold Time
Symbol tDS tDH
Min. 8 8
Typ.
Max
Unit nsec nsec
Conditions
(4) Reset Timing
RSTN
VIL
pRES
CLK
Parameter RSTN pulse width
Symbol pRES
Min. 100
Typ.
Max
Unit CLK
Conditions Rising Clock Edge
note ) Clock input is required for reset. Set RSTN pin to low after clock is fed. Output pins are in Hi-Z condition during RSTN pin at low. After reset is finished, decoded result is output if OE pin is at high ( Black level is output if no input is fed ).
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[ASAHI KASEI] (5) Power-down Sequence , Reset Sequence after the power-down release Activate reset for longer-than-512 clock time before setting PDN ( PDN to low ). Activate reset after the PDN release ( PDN to high ).
CLKIN ***********
AK8855
sRES
RSTN
hRES
VIH1, VIH2 VIL1, VIL2
PDN GND
VIH1, VIH2
Parameter RSTN pulse width time from PDN to high to RSTN to high
Symbol sRES hRES
Min. 512 10
Typ.
Max
Unit SYSCLK msec
At power-down, all control signals must be surely connected to either the selected power supply or ground level, and not to ViH / ViL levels. When to turn off power supplies ( AVDD / DVDD ) other than PVDD, set the device into the power-down condition after executing power-down sequence and then, the power should be turned off. It is recommended to set all digital output pins to PVDD potential or set OE pin high, in power-down mode setting. note ) clock input is required for reset operation. During reset sequence, output pins become Hi-Z condition ( it does not depend on OE pin state ). Power-down release sequence when crystal resonator is connected, is shown as follows.
AVDD/DVDD PVDD PDN RSTN
XTI VCOM,VRN,VRP
time till the stable oscillation of quartz crystal resonator, (not specified) design target value 5 ms ( max ). HRES => 10mS(min) PDN Release
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[ASAHI KASEI] AK8855 6) Power-On-Reset At power-on, reset must be enabled for a duration time till the Analog Reference Voltage & Current are stabilized. Power-on operation must be made with either simultaneous power-on of PVDD / AVDD / DVDD or PVDD first and then AVDD / DVDD
AVDD DVDD
2.7V
PVDD
1.6V
RSTN
VIL
pRES_PON
Parameter Symbol RESETN pulse width pRES_PON note ) clock input is required for reset operation.
Min. 10
Typ.
Max
Unit msec
Parameter
Power-On Sequence when crystal resonator is connected.
AVDD DVDD PVDD
RSTN
XTI
VCOM,VRN,VRP
time till the stable oscillation of quartz crystal resonator, (Not specified) design target value 5 ms ( max ).
pRES_PON =>10mS(min) Power Up
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[ASAHI KASEI] AK8855 (7) I2C Bus Input / Output Timing( DVDD / PVDD 2.7 V ~ 3.3 V or PVDD 1.6 V ~ 2.0 V, Ta = -30 ~ + 85 C ) (7-1) Timing 1
tBUF SDA tF SCL tLOW tSU:STA tHD:STA tR tF tSU:STO 0.7PVDD 0.3PVDD
tR
0.7PVDD 0.3PVDD
Parameter Symbol Min. Max. Unit Bus Free Time tBUF 1.3 usec Hold Time (Start Condition) tHD:STA 0.6 usec Clock Pulse Low Time tLOW 1.3 usec Input Signal Rise Time tR 300 nsec Input Signal Fall Time tF 300 nsec Setup Time(Start Condition) tSU:STA 0.6 usec Setup Time(Stop Condition) tSU:STO 0.6 usec The above I2C bus related timing is specified by the I2C Bus Specification, and it is not limited by the device performance. For details, please refer to the I2C Bus Specification. (7-2) Timing 2
tHD:DAT
SDA tHIGH
0.7PVDD 0.3PVDD
SCL tSU:DAT
0.7PVDD 0.3PVDD
Parameter Symbol Min. Max. Unit Data Setup Time tSU:DAT 100 (note1) nsec Data Hold Time tHD:DAT 0.0 0.9 (note2) usec Clock Pulse High Time tHIGH 0.6 usec note 1 : when to use I2C Bus Standard mode, tSU:DAT >- 250 ns must be met. note 2 : when the AK8855 is used in such bus interface where tLOW is not extended ( at minimum specification of tLOW ), this condition must be met.
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AK8855
Functional Outline
(1) Clock Feed a 24.5454 MHz clock. When a 27 MHz clock is required, it is generated by an internal PLL. Internal operating clock rates are : 24.5454 MHz at VGA / QVGA / rotated QVGA size / rotated CIF size outputs 27 MHz at 601 Pixel mode, CIF / QCIF Although clock is asynchronous with input signal, Vertical position is aligned since Digital Pixel Interpolator is integrated on-chip (2) Analog Interface The AK8855 accepts Composite Video signal. (3) Input Signal NTSC-M,PAL-B,-D, -G, -H, -I compatible Composite Video signals are accepted as input signal. (4) Analog Input Signal Processing Anti-aliasing filter is integrated on-chip. PGA : 0 dB ~ 12 dB ( approximately 0.1 dB / step ) AD Converter : operation at either 24.5454 MHz or 27.00 MHz (5) Clamp Processing Sync-Tip Clamping is processed in Analog part and Digital Pedestal Clamping in Digital Signal Processing part. (6) Adaptive AGC Function Based on the difference between the Sync-Tip level and Pedestal level, input signal value is corrected to a proper level. A function to adjust gain by Video signal level is integrated for such a case where only the Video signal is larger. (7) ACC Function Based on the Color Burst level, input Color signal level is corrected to a proper level. (8) Y / C Separation Function Primary Y / C separation is done. (9) Pixel Interpolator The AK8855 has an on-chip Digital Pixel Interpolator to align output pixels' vertical position. Therefore no line-synchronized clock etc are required. (10) Picture Quality Adjustment Function Adjustments of Contrast, Brightness, Color Hue and Color Saturation levels are possible. (11) Output Interface Outputs are ITU-R BT.601 compatible signal levels ( with limit ON / OFF ). Output interfaces are shown as follows : - supporting Camera I / F - ITU-R BT.656-like output format * - Active Video region is indicated by HD / VD ( FIELD ) / DVALID * with SAV / EAV, at 27 MHz output. There is a case where number of clock count from EAV to SAV may differ from Rec.656 format.
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[ASAHI KASEI] (12) Output Picture Size - VGA ( 640 X 480 ) ( interlaced output ) - QVGA ( 320 X 240 ) - CIF ( 352 X 288 ) - QCIF ( 176 X 144 ) - 601 ( NTSC : 720 X 480 / PAL : 720 X 576 ) ( interlaced output ) - rotated QVGA ( 240 X 180 ) - rotated CIF ( 288 X 216 )
AK8855
(13) Other Functions - Black level signal ( Y = 16, Cb / Cr = 128 ) is output in self-operating mode when no signal is input. - No signal input detection function - I2C Host interface - Power-down function - decoding function of Closed Caption, VBID ( CGMS-A 525 line ), WSS signal ( 625 line signal ). CRCC which is added to CGMS-A is decoded by the AK8855.
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AK8855
Input Signal
Decodable Video signals by the AK8855 are, - NTSC - PAL-B, -D, -G, -H, -I. Those input signal types are set by Input Video Standard Register ( R/W ) [ Sub Address 0x00]. Input signal is converted into digital code as follows. Clamp Block ---Anti-aliasing Filter ---PGA Block ---ADC Block
Then the digitized signal is signal-processed in digital block. Setting of Input Video Standard Register ( R/W ) [ Sub Address 0x00 ] is described here. This register is the setting register to set input signal attribute. Bit allocation of the register is as follows. Sub Address 0x00 bit 7 bit 6 Reserved Reserved 0 0 Default Value : 0x00 bit 1 bit 0 VSCF1 VSCF0 0 0
bit 5 Reserved 0
bit 4 bit 3 AINSEL VLF Default Value 0 0
bit 2 VCEN 0
[ VSCF1 : VSCF0 ]-bit setting of input signal sub-carrier is made by [ VSCF1 : VSCF0 ]-bit. Sub-carrier [VSCF1:VSCF0]-bit frequency Conditions [MHz] [00] 3.57954545 NTSC [01] 3.57561188 [10] 3.582054 [11] 4.43361875 PAL-B,D,G,H,I [ VCEN ]-bit setting of input signal Color Encoding system is set by [ VCEN]-bit.
[VCEN]-bit 0 1 Color Encoding system NTSC PAL Conditions
[ VLF]-bit setting of number of lines per each Frame of input signal is made by [ VLF]-bit. Conditions [VLF]-bit Number of lines 0 525 lines 1 625 lines [ AINSEL ]-bit selection of input signal is made. [AINSEL]-bit Input signal 0 AIN1 input is selected 1 AIN2 input is selected
Conditions
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AK8855
PGA ( Programmable Gain Amp )
PGA ( Programmable Gain Amp ) is integrated at the input stage of the AK8855. PGA is adjustable from 0 dB to 12 dB, and its gain step is approximately 0.1 dB / step. Signal input to the AK8855 is attenuated to 50 % level by a resistor-divider. PGA setting is made by PGA Control Register ( R/W ) [ Sub Address 0x05 ]. By writing "1" to Control Register ( R/W ) [ Sub Address 0x04 ] AGC-bit, AGC function is enabled. Since the set value by AGC is written at PGA Control Register ( R/W ) [ Sub Address 0x05 ], the AGC set value is known by reading this register ( manual setting of PGA is invalid ). When AGC function is disabled, PGA gain setting by manual is possible. Bit allocation of PGA Control Register is as follows. [ PGA Control Register ] Sub Address 0x05 bit 7 bit 6 Reserved PGA6 0 1
bit 5 PGA5 0
bit 4 bit 3 PGA4 PGA3 Default Value 0 0
bit 2 PGA2 1
Default Value: 0x46 bit 1 bit 0 PGA1 PGA0 1 0
AGC
The AK8855 has an adaptive AGC function. When AGC is enabled, input signal is controlled to a optimized level by PGA. When AGC is turned off, gain setting of PGA by manual is possible. Enable / disable setting of AGC is done by Control Register ( R/W ) [ Sub Address 0x04 ]. Sub Address 0x04 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CNTSEL DTFIX ODEV FRMRT1 FRMRT0 COLKIL ACC AGC Default Value 0 0 0 0 0 0 0 0 [ AGC ]-bit [ AGC ]-bit sets the mode of AGC [AGC]-bit Fumction Condition 0 Disable 1 Enable note ) writing into PGA register is possible while AGC is enabled, but the written result is not valid to register. The written result becomes valid to register when AGC is disabled.
Clamp
Input signal is Analog Sync-Tip clamped. The Sync-Tip clamped input signal is then clamped to Pedestal level after AD conversion.
Anti-Aliasing Filter
Analog Band Limit Filter is integrated before ADC input in the AK8855. The Anti-Aliasing Filter has following characteristics. +/-2.0dB (~5.5MHz) 27MHz -30dB ( typ )
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AK8855
Clock
Sampling is done by a fixed clock in the AK8855. PLL to synchronize with Analog input signal is not built-in. Clock rate differs depending on the selected output picture sizes and types of input signal. Internal operating clock is either 24.5454 MHz input clock or 27 MHz which is generated from input clock by PLL. Internal clock to be used is automatically selected by setting output picture size. operation clock 24.5454MHz 24.5454MHz 27MHz 27MHz 27MHz 27MHz Size 640 x 480 320 x 240 352 x 288 176 x 144 720 x 480 720 x 576 Signal NTSC/PAL NTSC/PAL NTSC/PAL NTSC/PAL NTSC PAL Note Interlace output Progressive output Progressive output Progressive output Interlace output Interlace output
VGA QVGA CIF QCIF 601
Rotated 24.5454MHz 240 x 180 NTSC/PAL Progressive output QVGA Rotated CIF 24.5454MHz 288 x 216 NTSC/PAL Progressive output note ) In case of the rotated CIF size, both left-end and right-end 16 pixels are omitted and 288 X 216 picture size is output ( 90% area of the effective picture is output ). When decoding CIF ( NTSC ), output rate is 2X speed of input HD.
Output Picture Size
Setting of output picture size is done by [ OFORM2 : OFORM0 ]-bit of Output Control 1 Register ( R/W ) [ Sub Address 0x01 ]. Setting is as follows. [OFORM2:OFORM0]-bit [OFORM2:OFROM0]-bit 000 001 010 011 100 101 110 Function QVGA VGA CIF QCIF Rotated QVGA Rotated CIF 601 Condition
Decimation Filter
Characteristic of Decimation Filter is shown as follows ( shown below is a characteristic at 27 MHz sampling ).
Frequency [MHz] 5.0 6.0 7.0 8.0
0.0 10.0 0.0 -10.0 Gain [dB] -20.0 -30.0 -40.0 -50.0 -60.0
1.0
2.0
3.0
4.0
9.0 10.0 11.0 12.0 13.0
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AK8855
Sync-Separation, Sync-Detection
Sync-Detection and Separation are made from the digitized input signal. The recognized Sync-signal is used as reference timing for decoding process.
Digital Pedestal Clamp
Converted input signal into digital code clamps the pedestal part. Internal clamp levels differ depending on types of input signals ( 286mV Sync signal and 300 mV Sync signal ), but output result operates such that pedestal position becomes at code 16 ( 8-bit Rec. 601 level ) for either case.
YC Separation
YC separation is done in a primary YC separation mode in the AK8855. Filter characteristic used for YC separation is as follows ( shown below is a characteristic at 27 MHz sampling ).
10 0 -10 Gain[dB] -20 -30 -40 -50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
frequency[MHz]
Auto Color Control ( ACC )
This is a function to adjust Color Burst level of input signal to a proper level ( NTSC : 286 [mV] / PAL : 300 [mV] ). Input Color signal level is decided by Color Burst signal. ACC gain is 20 dB maximum. Sub Address 0x04 bit 7 bit 6 CNTSEL DTFIX 0 0 Default Value: 0x00 bit 1 bit 0 ACC AGC 0 0
bit 5 ODEV 0
bit 4 bit 3 FRMRT1 FRMRT0 Default Value 0 0
bit 2 COLKIL 0
[ ACC ]-bit [ ACC ]-bit selects enable / disable of ACC and time constant. [ACC]-bit ACC Setting 0 Disable 1 Enable
Condition
ACC function operates independently from Color Saturation Adjust function ( when ACC is enabled, Color Saturation adjustment is made on the signal which is adjusted to a proper level by ACC ).
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AK8855
Color Killer
Chroma Signal Quality is decided by Color Burst level of input signal. When the Chroma Signal level is lower than a threshold level, it is decided to be improper signal and input signal is all processed as luminance signal. In this case, Cb / Cr data from the AK8855 is a fixed 0x80 in 601 level. Color Killer functions when Color Burst level becomes lower than approximately -23 dB. Bit allocation of Control Register ( R/W ) [ Sub Address 0x04 ] is as follows. Sub Address 0x04 bit 7 bit 6 CNTSEL DTFIX 0 0 Default Value: 0x00 bit 1 bit 0 ACC AGC 0 0
bit 5 ODEV 0
bit 4 bit 3 FRMRT1 FRMRT0 Default Value 0 0
bit 2 COLKIL 0
[ COLKILL ]-bit [ COLKILL ]-bit selects enable / disable of Color Killer function. COLKILL-bit Color Killer Function 0 Enable 1 Disable
Condition
Frame Rate setting
This is to set the Frame Rate. Frame Rate setting is done by [ FRMRT1 : FRMRT0 ]-bits of Control Register ( R/W ) [ Sub Address 0x04 ]. [FRMRT1:FRMRT0]-bit 00 01 10 11 Frame Rate 30/25(525/625) 15/12.25(525/625) 7.5/6.25(525/625) Reserved Condition
Even / Odd Field selection
Even / Odd Field setting is done for QVGA / CIF / QCIF output modes. Setting is done by [ODEV ]-bit of Control Register ( R/W ) [ Sub Address 0x04 ]. ODEV-bit 0 1 Condition ODD Field EVEN Field
Power Saving Mode at Low Frame Rate
Power dissipation during no-output period is reduced when Frame Rate is dropped. Setting is done by [ DTFIX ]-bit of Control Register ( R/W ) [ Sub Address 0x04 ]. DTFIX-bit 0 1 Power Saving mode Disabled Enable Condition
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AK8855
UV Filter
UV Filter characteristic is as follows.
Picture Quality Adjust Process Function
Those Picture Quality Adjust processing such as Contrast adjust function, Brightness adjust function, Color Saturation adjust function and Color Hue adjust function are integrated in the AK8855. (1) Contrast Adjust Function Contrast Adjustment is processed by multiplying Luminance signal ( Y ), by the gain value which is set by Contrast Control Register ( R/W ) [ Sub Address 0x06 ]. CNTSEL-bit = 0 YOUT = CONT* ( YIN - 128 ) + 125 ; YOUT YIN CONT : Contrast arithmetic operation result : before Contrast arithmetic operation : Contrast coefficient ( register set value )
It is also possible to define the equation as follows by register setting CNTSEL-bit = 1 YOUT = CONT* ( YIN - 128 ) + 16 ; YOUT : Contrast arithmetic operation result YIN : before Contrast arithmetic operation CONT : Contrast coefficient ( register set value ) Setting is made by [ CNTSEL ]-bit of Control Register ( R/W ) [ Sub Address 0x04 ]. Variable range of Contrast Gain coefficient is from 0 to 1.99 ( 1 / 128 step ) and when the arithmetic operation result exceeds the above range, it is clipped to the upper-limit of [ 254 ], or the lower-limit of [ 1 ] ( output result ranges from 16 to 235 when 601 Limit-bit is at [ 1 ] ). Bit allocation of Contrast Control Register is as follows. Sub Address 0x06 bit 7 bit 6 bit 5 bit 4 bit 3 CONT7 CONT6 CONT5 CONT4 CONT3 Default Value 1 0 0 0 0 Sub Address 0x04 bit 7 bit 6 CNTSEL DTFIX 0 0
bit 2 CONT2 0
Default Value: 0x80 bit 1 bit 0 CONT1 CONT0 0 0
bit 5 ODEV 0
bit 4 bit 3 FRMRT1 FRMRT0 Default Value 0 0
bit 2 COLKIL 0
Default Value: 0x00 bit 1 bit 0 ACC AGC 0 0
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[ASAHI KASEI] [ CNTSEL ]-bit [ CNTSEL ]-bit sets the change-over point of Contrast adjustment. [CNTSEL]-bit Function 0 To be adjusted at Luminance 125 as a center point 1 To be adjusted at Luminance 16 as a center point.
AK8855
Condition
(2) Brightness Adjust Function Brightness Adjust function is processed by adding to the Luminance signal ( Y ), a value which is set by Brightness Control Register ( R/W ) [ Sub Address 0x07 ]. YOUT = YIN + BR YOUT YIN BR : Brightness arithmetic operation result : before Brightness arithmetic operation : Brightness coefficient ( register set value )
Variable range of Brightness adding coefficient is from - 127 to +127 and the value setting is made in 2's complement number. When the arithmetic operation result exceeds the above range, it is clipped to the upper-limit of [ 254 ], or the lower-limit of [ 1 ] ( output result ranges from 16 to 235 when 601 Limit-bit is at [ 1 ] ). Bit allocation of Brightness Control Register is as follows. Sub Address 0x07 bit 7 bit 6 bit 5 bit 4 bit 3 BR7 BR6 BR5 BR4 BR3 Default Value 0 0 0 0 0
bit 2 BR2 0
Default Value: 0x00 bit 1 bit 0 BR1 BR0 0 0
(3) Color Saturation Adjust Function Color Saturation adjustment is processed by multiplying the Color Signal ( C ), by a value which is set by Saturation Control Register ( R/W ) [ Sub Address 0x08 ]. Saturation coefficient is processed over C signal. A multiplied result by Saturation coefficient is U / V de-modulated. Variable range of Saturation multiplying coefficient is from 0 to 255 / 128 in 1 / 128 programmable step. The default value of the register is un-adjusted value ( 0x80 ). Bit allocation of Saturation Control Register is as follows. Sub Address 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 SAT7 SAT6 SAT5 SAT4 SAT3 Default Value 1 0 0 0 0
bit 2 SAT2 0
Default Value: 0x80 bit 1 bit 0 SAT1 SAT0 0 0
(4) Color Hue Adjust Function The Color Hue can be rotated in the AK8855. Rotation amount of Color Hue depends on a value which is set by HUE Control Register ( R/W ) [ Sub Address 0x09 ]. Variable Rotation range of the phase is +/- 45 degrees ( in approximately 0.35 degree / step ). Default value of the register is un-adjusted value ( 0x00 ). Set value is made in 2's complement number. Bit allocation of Hue Control Register is as follows. Sub Address 0x09 bit 7 bit 6 bit 5 bit 4 bit 3 HUE7 HUE6 HUE5 HUE4 HUE3 Default Value 0 0 0 0 0
bit 2 HUE2 0
Default Value: 0x00 bit 1 bit 0 HUE1 HUE0 0 0
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AK8855
Input Video Decoding Period
This defines Decoding process period of input Video signal. The period defined here is for the input Video source. As for the decode data, a number of Lines differs, depending on the selected output mode. Refer to a figure at next page which shows " Input Video Signal vs Output Data relation ". Active Video Period is as follows. 525 Line system : Line 22 ~ Line 261 & Line 285 ~ Line 524 625 Line system : Line 23 ~ Line 310 & Line 336 ~ Line 623 Vertical Blanking Period is as follows . 525 Line system : Line 525 ~ Line 1 ~ Line 21 & Line 262 ~ Line 284 625 Line system : Line 624 ~ Line 625 - Line1 ~ Line 22 & Line 311 ~ Line 335 Default value of output during Vertical Blanking period is Black level ( Y = 0x10, Cb / Cr = 0x80 ).
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AK8855
Closed Caption / Closed Caption Extended Data / VBID ( CGMS ) / WSS
Closed Caption data, Closed Caption Extended data, VBID ( CGMS ) and WSS signals which are super-imposed during VBI interval are decoded in the AK8855. Decoded data is written into register. When Request bits [ bit3 : bit 0 ] of Request VBI Info Register ( W ) [ Sub Address 0x0A] are set, the AK8855 judges that a decode request of each data is made and it is put into data wait condition. After data is detected and decoded, it informs to the Host, using [ bit3 : bit 0 ] of Macrovision Status Register that decoding has been completed. Decoded results are written into Closed Caption 1 Register ( R ) [ Sub Address 0x12 ] / Closed Caption 2 Register ( R ) [ Sub Address 0x13 ], Extended Data 1 Register ( R ) [ Sub Address 0x14 ] / Extended Data 2 Register ( R ) [ Sub Address 0x15 ], VBID / WSS1 Register ( R ) [ Sub Address 0x16 ] / VBID / WSS2 Register ( R ) [ Sub Address 0x17 ] respectively. Each data is super-imposed on the respective Line as listed below. CRCC code of VBID data ( CGMS-A ) is decoded and its result only is stored in register. Signal Closed Caption Closed Caption Extended VBID WSS Line NTSC : Line-21 NTSC : Line-284 NTSC : Line-20/283 PAL : Line-23 Note 525-Line 525-Line 525-Line 625-Line
Configuration of Request VBI INFO Register is as follows. Sub Address 0x0A bit 7 bit 6 bit 5 bit 4 bit 3 Reserved Reserved Reserved Reserved Reserved Default Value 0 0 0 0 0 Configuration of Status Register is as follows Sub Address 0x10 bit 7 bit 6 bit 5 bit 4 VBWSSDE EXTDET CCDET AGCSTS T
bit 2 VBWSRQ 0
Default Value: 0x00 bit 1 bit 0 EXTRQ CCRQ 0 0
bit 3 CPLLLCK
bit 2 PKWHITE
bit 1 COLKILST
bit 0 NSIG
Information Read-Out Flow during VBI interval is shown below.
Start
[ Request VBI Info Register ] xxRQ-bit = 1 ( Decode Request )
Closed Caption: CCRQ-bit Closed Caption Extended : EXTRQ-bit VBID/WSS: VBWSRQ-bit
[ Status Register ] Read ( Verif ication of decode completion )
( Corresponding bit is "1" to the request ? ) Yes ( Read-out of the corresponding data register to the request )
No Closed Caption: CCDET-bit Closed Caption Extended : EXTDET-bit VBID/WSS: VBWSDET-bit Closed Caption: [Closed Caption 1/2 Register] Closed Caption Extended : [Extended Data 1/2 Register] VBID/WSS: [VBID/WSS 1/2 Register]
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[ASAHI KASEI] AK8855 When to read out Closed Caption data : Write "1" to CCRQ-bit of Request VBI Info Register ( W ) [ Sub Address 0x0A ]. When "1" is written to this bit, the AK8855 is put into a wait condition for Closed Caption Data decoding. Then when Data comes in, it is decoded and after the decoding, "1" is written back to CCDET-bit of Status Register ( R / W ) [ Sub Address 0x10 ]. CCDET-bit right after Reset, is "1" ( it becomes "0" when "1" is written to CCRQ-bit ). Decoded result is written into Closed Caption 1 Register ( R ) [ Sub Address 0x12 ] and Closed Caption 2 Register ( R ) [ Sub Address 0x13 ] as shown next. Data in Closed Caption 1 Register and Closed Caption 2 Register are retained till they are over-written with new data. Configuration of Closed Caption 1 Register and Closed Caption 2 Register are as follow. Closed Caption 1 Register (R) [Sub Address 0x12] Sub Address 0x12 bit 7 bit 6 bit 5 bit 4 CC7 CC6 CC5 CC4
bit 3 CC3
bit 2 CC2
bit 1 CC1
bit 0 CC0
Closed Caption 2 Register (R) [Sub Address 0x13] Sub Address 0x13 bit 7 bit 6 bit 5 bit 4 bit 3 CC15 CC14 CC13 CC12 CC11
bit 2 CC10
bit 1 CC9
bit 0 CC8
When to read out Closed Caption Extended Data : Write "1" to EXTRQ-bit of Request VBI Info Register ( W ) [ Sub Address 0x0A ]. When "1" is written to this bit, the AK8855 is put into a wait condition for Extended Data decoding. Then, when data comes in, it is decoded and after the decoding, "1" is written back to EXTDET-bit of Status Register ( R / W ) [ Sub Address 0x10 ]. EXTDET-bit right after the Reset, is "1" ( it becomes "0" when "1" is written to EXTRQ-bit ). Decoded result is written into Extended Data 1 Register ( R ) [ Sub Address 0x14 ] and Extended Data 2 Register ( R ) [ Sub Address ox15 ] as shown next. Data in Extended Data 1 Register and Extended Data 2 Register are retained till they are over-written with new data. Configuration of Extended Data 1 Register and Extended Data 2 Register are as follow. Extended Data 1 Register (R) [Sub Address 0x14] Sub Address 0x14 bit 7 bit 6 bit 5 bit 4 EXT7 EXT6 EXT5 EXT4
bit 3 EXT3
bit 2 EXT2
bit 1 EXT1
bit 0 EXT0
Extended Data 2 Register (R) [Sub Address 0x15] Sub Address 0x15 bit 7 bit 6 bit 5 bit 4 bit 3 EXT15 EXT14 EXT13 EXT12 EXT11
bit 2 EXT10
bit 1 EXT9
bit 0 EXT8
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[ASAHI KASEI] When to read out VBID Data :
AK8855
Write "1" to VBWSRQ-bit of Request VBI Info Register ( W ) [ Sub Address 0x0A ]. When "1" is written to this bit, the AK8855 is put into a wait condition for VBID data decoding. Then when data comes in, it is decoded and after the decoding, "1" is written back to VBWSDET-bit of Status Register ( R / W ) [ Sub Address 0x10 ]. VBWSDET-bit right after reset, is "1" ( it becomes "0" when "1" is written to VBWSRQ-bit ). Decoded data is 13 Bit-long and it is written into VBID / WSS1 Register ( R ) [ Sub Address 0x16 ] and VBID / WSS 2 Register ( R ) [ Sub Address 0x17 ]. VBID data is valid only in 525 Line system. These registers are also commonly used for WSS Read-Out register. CRCC code is decoded and its data only is stored in register. Data in VBID / WSS 1 Register and VBID / WSS 2 Register are retained till they are over-written with new data. Configuration of VBID / WSS 1 Register and VBID / WSS 2 Register are as follow. VBID/WSS 1 Register (R) [Sub Address 0x16] Register to store VBID data Sub Address 0x16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Reserved Reserved VBID1 VBID2 VBID3 VBID4
bit 1 VBID5
bit 0 VBID6
VBID/WSS 2 Register (R) [Sub Address 0x17] Register to store VBID data Sub Address 0x17 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 VBID7 VBID8 VBID9 VBID10 VBID11 VBID12 VBID13 When to read out WSS Data :
bit 0 VBID14
Write "1" to VBWSRQ-bit of Request VBI Info Register ( W ) [ Sub Address 0x0A ]. When "1" is written to this bit, the AK8855 is put into a wait condition for VBWS data decoding. Then when data comes in, it is decoded and after the decoding, "1" is written back to VBWS-bit of Status Register ( R / W ) [ Sub Address 0x10 ]. VBWS-bit right after reset, is "1" ( it becomes "0" when "1" is written to VBWSRQ-bit ). WSS data is valid only in 625 Line system. These registers are also commonly used for VBID Read-Out register. Decoded results are written into VBID / WSS 1 Register ( R ) [ Sub Address 0x16 ] and VBID / WSS 2 Register ( R ) [ Sub Address 0x17 ] as shown next. Data in VBID / WSS 1 Register and VBID / WSS 2 Register are retained till they are over-written with new data. VBID/WSS 1 Register (R) [Sub Address 0x16] Register to store WSS data Sub Address 0x16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Reserved Reserved G4-13 G4-12 G4-11 G3-10 VBID/WSS 2 Register (R) [Sub Address 0x17] Register to store WSS data Sub Address 0x17 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 G2-7 G2-6 G2-5 G2-4 G1-3 G1-2
bit 1 G3-9
bit 0 G3-8
bit 1 G1-1
bit 0 G1-0
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AK8855
Macrovision Decoding
When Macrovision Copy Protect signal is input, the AK8855 decodes the added Macrovision information and stores the result at Macrovision Status Register ( R/W ) [ Sub Address 0x11 ]. Configuration of Macrovision Status Register is as follows. Sub Address 0x11 bit 7 bit 6 Reserved PSPDET bit 5 AGCPDET bit 4 BPPDET bit 3 SYNCRED bit 2 CSTYPE bit 1 CSDET bit 0 AGCDET
[ AGCDET ]-bit When Macrovision AGC process is recognized, this bit becomes "1". [AGCDET]-bit Status of Macrovision Detection 0 AGC Process in not detected 1 AGC Process is detected [ CSDET ]-bit When Macrovision Color Stripe Process is recognized, this bit becomes "1". [CSDET]-bit Status of Macrovision Detection 0 Color Stripe Process is not detected 1 Color Stripe Process is detected [ CSTYPE ]-bit When CSDET-bit is "1", Color Stripe Process type is indicated. [CSTYPE]-bit Status of Macrovision Detection 0 Color Stripe Type 2 is set 1 Color Stripe Type 3 is set [ SYNCRED ]-bit When SYNCRED-bit is "1", it indicates that Sync Reduction has been detected. [SYNCRED]-bit Status of Macrovision Detection 0 1 Sync Reduction is detected
Condition
Condition
Condition
Condition
[ BPPDET ]-bit When BPPDET-bit is "1", it indicates that " End of Field Back Porch Pulse " has been detected. [BPPDET]-bit Status of Macrovision Detection Condition 0 1 End of Field Back Porch Pulse is detected [ AGCPDET ]-bit When AGCPDET-bit is "1", it indicates that AGC Pulse has been detected. [AGCPDET]-bit Status of Macrovision Detection 0 1 AGC Pulse is detected [ PSPDET ]-bit When PSPDET-bit is "1", it indicates that Pseudo Sync Pulse has been detected. [PSPDET]-bit Status of Macrovision Detection 0 1 Pseudo Sync Pulse is detected.
Condition
Condition
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AK8855
Decode Data Output ( Rec. 601 Limit )
The AK8855 outputs the decode data at the specified level ( Y / Cb / Cb 4:2:2 ) by ITU-R BT.601. Min. / Max. output data can be selected by [ LIMIT601 ]-bit of Output Control 1 Register ( R/W ) [ Sub Address 0x01 ]. Bit allocation of Output Control 1 Register is as follows. Sub Address 0x01 bit 7 bit 6 VDPSUP TRSVSEL 0 0 bit 5 OIF1 0 bit 4 bit 3 OIF0 LIMIT601 Default Value 0 0 bit 2 OFORM2 0 Default Value : 0x00 bit 1 bit 0 OFORM1 OFORM0 0 0
[ LIMIT601 ]-bit Min. / Max. of Output Data is specified by [ LIMIT601 ]-bit. All internal, arithmetic operations are processed at Min. = 1, Max. = 254. Clipping value of Output code differs by [ LIMIT601 ] -bit setting. Default value setting is "0". [LIMIT601]-bit 0 1 Output code Min.Max Y : 1 ~ 254 Cb/Cr : 1 ~ 254 Y : 16 ~ 235 Cb/Cr : 16 ~ 240 Condition ( Default value )
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AK8855
Output Interface
The AK8855 supports 3 types of Interfaces. (1) Camera Interface ( QVGA / CIF / QCIF ) (2) Interface by HD / VD / DVALID ( VGA / QVGA / CIF / QCIF ) (3) 656 Interface ( 601 specification compatible size ( 720 X 480 )) Timing diagrams of each output mode are shown in each output mode description section. The AK8855 outputs data ( D [ 7:0 ] ) and output timing signals ( HD / HV, VD / VAF, DVALID , FIELD ) in accordance with the specified timing diagram only when either of the following conditions is met : (a) when the AK8855 operation is in sync with input signal, (b) when the AK8855 cannot establish synchronization with input signal and it is decided that no signal is input ( Black signal output at default condition ). During transition from condition (a) to condition (b) or from condition (b) to condition (a), specified data ( D [ 7:0 ]) and output timing signals ( HD / HV, VD / VAF, DVALID, FIELD ) may differ from the one shown in the specified timing diagram. (1) Camera Interface There are 2 types of data interface - " (1-1) HV & VAF Interface Mode " and " (1-2) SAV / EAV Interface Mode ". In this mode, since shift of synchronization with the input signal is adjusted at the head part of Line, interval between Lines may fluctuate in some degree. When an exceptional input signal is decoded, there may be cases where lack of # of Lines and lack of # of Pixels per Line occur, regardless of operation mode. At the default value, end of Frame is made at the rising edge of VAF signal, and end of Line is made by HV signal. Polarity of VAF / HV / DVALID / CLKO is programmable by Output Control 2 Register ( R/W ) [ Sub Address 0x02 ]. Following timing diagrams show operation examples at HDP = 0, VDP = 0, DVALDP = 0, CLKINV = 1 settings. Since output is Progressive Output in Camera Interface mode, picture sizes to be handled in this mode are QVGA / CIF / QCIF / rotated QVGA / rotated CIF. Definition of SAV / EAV at section (1-2) SAV / EAV Interface Mode is as follows. SAV 0x80 0xAB EAV 0x9D 0xB6
Active VBlank
In SAV / EAV Output mode, HV / VAF signal is not output at default value. It is possible to output by setting register.
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[ASAHI KASEI] (1-1) Interface by HV / VAF Following timing diagram shows CIF size output case as an example.
VD/VAF
AK8855
HD/HV
****** Line288
Line1
Line2
Line3
Line4
Line1
Line2
D/CDT[7:0]
CLKO
HD/HV
Cb175
Cr175
Y351
D/CDT[7:0]
******
Cb0
Cb1
Cb2
Cr0
Cr1
Y0
Y1
Y2
Y3
Y4
CLKO
******
(1-2) Interface by SAV / EAV ( CIF size output example )
VD/VAF
HD/HV active SAV
******
VBlank SAV
Blank Line Line288 Line287 Line4 Line1
Line1
Line2
Line3
D/CDT[7:0]
active EAV CLKO
VBlank EAV
HD/HV D/CDT[7:0]
Cb175
Cr175
Y351
0xFF
0xFF
0x00
0x00
0x00
0x00
SAV
EAV
******
Cb0
Cb1
Cr0
Y0
Y1
Y2
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[ASAHI KASEI] Output Timings of Camera I/F mode are shown as follows. ( The polarity of HV/VAF/DVALID can be changed by register setting. )
AK8855
NTSC
Line # VD/VAF HV
(QVGA)
Register: VLF = 1'b0, OIF[1:0] = 2'b10
3 4 5 6 7 ... 21 22 23 24 25 26 27 28 29 30 31 ... 258 259 260 261 262 263 264 265
HV
(VGA)
HV
(CIF)
HV
(QCIF)
HV
(QVGAL)
HV
(CIFL)
HV
(601)
Line # VD/VAF HV
(QVGA)
266
267
268
269
270
...
284
285
286
287
288
289
290
291
292
293
294
...
521
522
523
524
525
1
2
3
HV
(VGA)
HV
(CIF)
HV
(QCIF)
HV
(QVGAL)
HV
(CIFL)
HV
(601)
Note: In case of the output mode except VGA, 601, DVALID signal becomes active(Low) either ODD or EVEN timing. The timing chart is shown the both case for the sake of convenience. QVGAL: Rotated QVGA, CIFL: Rotated CIF
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[ASAHI KASEI]
AK8855
PAL
Line # VD/VAF HV
(QVGA)
Register Set : VLF = 1'b1, OIF[1:0] = 2'b10
625 1 2 3 4 ... 22 23 24 25 26 27 28 29 30 31 32 ... 307 308 309 310 311 312 313 314
HV
(VGA)
HV
(CIF)
HV
(QCIF)
HV
(QVGAL)
HV
(CIFL)
HV
(601)
Line # VD/VAF HV
(QVGA)
313
314
315
316
317
...
335
336
337
338
339
340
341
342
343
344
345
...
620
621
622
623
624
625
1
2
HV
(VGA)
HV
(CIF)
HV
(QCIF)
HV
(QVGAL)
HV
(CIFL)
HV
(601)
Note: In case of the output mode except VGA, 601, DVALID signal becomes active(Low) either ODD or EVEN timing. The timing chart is shown the both case for the sake of convenience. QVGAL: Rotated QVGA, CIFL: Rotated CIF
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[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
QVGA (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 318
Y 318
Cr318
Y 319
0x80
0x80
640 clock @CLKO
Timing Chart (Camera I/F)
VGA (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(24.5454MHz)
H L H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 318 Y 636 Cr318 Y 637 Cb 319 Y 638 Cr319 Y 639 0x80 0x10
0x80 0x10
1280 clock @CLKO
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[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
CIF (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b00
HV VAF DVALID
(27.0MHz)
H L H
CLKO
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 348 Y 348 Cr348 Y 349 Cb 350 Y 350 Cr350 Y 351 0x80 0x10
0x80 0x10
704 clock @CLKO
In case of NTSC, CIF output mode, 2 Lines are output while the 1 line input. HD/VD signal are also output doubled rate.
Timing Chart (Camera I/F)
QCIF (NTSC)
Register Set : VLF = 1'b0, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b00
HV VAF DVALID
(6.75MHz)
H L H
CLKO
D[7:0]
Cb 0
Y0
Cb 174
Y 174
Cr174
Y 175
0x80
0x80
352 clock @CLKO HD CLKO
(6.75MHz)
H
In case of QCIF, there is a possibility that the Low period of CLKO signal just before the HV falling edge becomes 1.5 longer than usual case as left chart. Even in this case, falling edge of HV and falling edge of CLKO is same timing.
MS0319-E-03
35
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
Rotated QVGA (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 238
Y 238
Cr238
Y 239
0x80
0x80
480 clock @CLKO
Timing Chart (Camera I/F)
Rotated CIF (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 286
Y 286
Cr286
Y 287
0x80
0x80
576 clock @CLKO
MS0319-E-03
36
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
601Output (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b110, OIF[1:0] = 2'b00
HV VAF DVALID
(27.0MHz)
H L H
CLKO
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 716 Y 716 Cr716 Y 717 Cb 718 Y 718 Cr718 Y 719 0x80 0x10
0x80 0x10
1440 clock @CLKO
MS0319-E-03
37
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
0x10
Cb 0
Y0
Cb 318
Y 318
Cr318
Y 319
0x80
0x80
640 clock @CLKO
Timing Chart (Camera I/F)
VGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(24.5454MHz)
H L H
D[7:0]
0x10
Cb 0
Y0
Cb 319
Y 638
Cr319
Y 639
0x80
0x80
1280 clock @CLKO
MS0319-E-03
38
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
CIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b00
HV VAF DVALID
(13.5MHz)
H L H
CLKO
D[7:0]
Cb 0
Y0
Cb 175
Y 350
Cr175
Y 351
0x80
0x80
704 clock @CLKO
Timing Chart (Camera I/F)
QCIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b00
HV VAF DVALID
(6.75MHz)
H L H
CLKO
D[7:0]
Cb 0
Y0
Cb 87
Y 174
Cr87
Y 175
0x80
0x80
352 clock @CLKO HD CLKO
(6.75MHz)
H
In case of QCIF, there is a possibility that the Low period of CLKO signal just before the HV falling edge becomes 1.5 longer than usual case as left chart. Even in this case, falling edge of HV and falling edge of CLKO is same timing.
MS0319-E-03
39
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
Rotated QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(12.2727MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 119
Y 238
Cr119
Y 239
0x80
0x80
480 clock @CLKO
Timing Chart (Camera I/F)
Rotated CIF (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b00
HV VAF DVALID CLKO
(13.5MHz)
H L H
D[7:0]
Cb 0
Y0
Cb 143
Y 286
Cr143
Y 287
0x80
0x80
576 clock @CLKO
MS0319-E-03
40
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (Camera I/F)
601Output (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b110, OIF[1:0] = 2'b00
HD/HV VAF DVALID
(27.0MHz)
H L H
CLKO
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 358 Y 716 Cr358 Y 717 Cb 359 Y 718 Cr359 Y 719 0x80 0x10
0x80 0x10
1440 clock @CLKO
MS0319-E-03
41
2004 / 11
[ASAHI KASEI] AK8855 (2) Interface by HD / VD / DVALID Synchronization is made by HD / VD. DVALID signal which becomes active during active Video interval, is used. Since Even / Odd Field recognition is possible by HD / VD signal, interlace information is known. In the AK8855, data is output by DVALID signal which becomes active during active Video region. Relation between DVALID signal and data is shown in the following diagram ( example shown is at 27 MHz sampling ). DVALID signal which indicates active video interval, is output at the following timing shown below ( 601 output case ).
Video Signal
HD DVALID CLKO
D[7:0]
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
Y718 Cr359 Y719
Active Video Start position ( in normal operation, it is at 123th / 133th ( NTSC / P ) sampling, counting from 0h point )(601 mode ) AL
Timing Diagram is shown below.
CLKO
HD DVALID DATA[7:0] b a
FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 FF 00 00 EAV
( data FF0000SAV & FF0000EAV are at Rec.656 mode. For other than Rec.656 mode, they are replaced with 10H80H10H80H data ) 525-Line (VLF-bit = 0) 625-Line (VLF-bit = 1) Number of CLKO count Number of CLKO count a b CLKO Rate a b CLKO Rate QVGA 000 118 640 12.2727MHz 127 640 12.2727MHz VGA 001 236 1280 24.5454MHz 254 1280 24.5454MHz CIF 010 130 704 27.0MHz 140 704 13.5MHz QCIF 011 65 352 6.75MHz 70 352 6.75MHz Rotated QVGA 100 198 480 12.2727MHz 207 480 12.2727MHz Rotated CIF 101 150 576 12.2727MHz 159 576 12.2727MHz 601 110 244 1440 27MHz 264 1440 27.0MHz * note : output data rate of CIF size mode in 525 Line system ( NTSC ) is doubled. Mode [OFORM2:OFRO M0] Polarity of CLKO / HD / VD / DVALID is programmable by setting Output Control 2 Register ( R/W ) [ Sub Address 0x02 ]. Timing diagrams shown at next page and thereafter are for operation at HDP = 0, VDP = 0, DVALDP = 0, CLKINV = 1 settings.
MS0319-E-03
42
2004 / 11
[ASAHI KASEI] The relationship of HD/VD/DVALID are shown as follows. (The polarity of HD/VD/DVALID can be changed with register setting) NTSC Register Set: VLF = 1'b0, OIF[1:0] = 2'b10
Line # HD
(Except CIF)
AK8855
3
4
5
6
7
...
21
22
23
24
25
26
27
28
29
30
31
...
258
259
260
261
262
263
264
265
HD
(CIF)
VD VDALID
(QVGA)
VDALID
(VGA)
VDALID
(CIF)
VDALID
(QCIF)
VDALID
(QVGAL)
VDALID
(CIFL)
VDALID
(601)
Line # HD/HV
(Except CIF)
266
267
268
269
270
...
284
285
286
287
288
289
290
291
292
293
294
...
521
522
523
524
525
1
2
3
HD/HV
(CIF)
VD/VAF VDALID
(QVGA)
VDALID
(VGA)
VDALID
(CIF)
VDALID
(QCIF)
VDALID
(QVGAL)
VDALID
(CIFL)
VDALID
(601)
Note: In case of the output mode except VGA, 601, DVALID signal becomes active(Low) either ODD or EVEN timing. The timing chart is shown the both case for the sake of convenience. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0319-E-03
43
2004 / 11
[ASAHI KASEI]
AK8855
PAL
Line # HD/HV VD/VAF VDALID
(QVGA)
Register Set: VLF = 1'b1, OIF[1:0] = 2'b10
625 1 2 3 4 ... 22 23 24 25 26 27 28 29 30 31 32 ... 307 308 309 310 311 312 313 314
VDALID
(VGA)
VDALID
(CIF)
VDALID
(QCIF)
VDALID
(QVGAL)
VDALID
(CIFL)
VDALID
(601)
Line # HD/HV VD/VAF VDALID
(QVGA)
313
314
315
316
317
...
335
336
337
338
339
340
341
342
343
344
345
...
620
621
622
623
624
625
1
2
VDALID
(VGA)
VDALID
(CIF)
VDALID
(QCIF)
VDALID
(QVGAL)
VDALID
(CIFL)
VDALID
(601)
Note: In case of the output mode except VGA, 601, DVALID signal becomes active(Low) either ODD or EVEN timing. The timing chart is shown the both case for the sake of convenience. QVGAL: Rotated QVGA, CIFL: Rotated CIF
MS0319-E-03
44
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
QVGA (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b10
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
58 clock @CLKO 118 clock @CLKO
HD VD DVALID
(12.2727MHz)
H H H
CLKO
D[7:0]
Cb 0
Y0
Cb 159
Y 318
Cr159
Y 319
0x80
0x80
640 clock @CLKO
22 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
45
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
VGA (NTSC)
Register set: VLF = 1'b0, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b10
HD VD DVALID
(24.5454MHz)
H H H
CLKO D[7:0] xx xx 0x80 0x10 0x80 0x10 0x80 0x10 Cb 0 Y0 Cr0 Y1 Cb 1 Y2 Cr1 Y3 Cb 2 Y4
116 clock @CLKO 236 clock @CLKO
HD VD DVALID
(24.5454MHz)
H H H
CLKO D[7:0] 0x80 0x10 Cb 0 Y0 Cr0 Y1 Cb 318 Y 636 Cr318 Y 637 Cb 319 Y 638 Cr319 Y 639 0x80 0x10 0x80 0x10
1280 clock @CLKO
44 clock *@CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
46
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
CIF(NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b10
HD VD DVALID
(27.0MHz)
H H H
CLKO
D[7:0]
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 1
Y2
Cr1
Y3
Cb 2
Y4
128 clock @CLKO 130 clock @CLKO
HD VD DVALID CLKO
(27.0MHz)
H H H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 174 Y 348 Cr174 Y 349 Cb 175 Y 350 Cr175 Y 351 0x80 0x10
0x80 0x10
704 clock @CLKO
24 clock* @CLKO
*This value is not guaranteed. Just reference value.
In case of NTSC and CIF output mode, 2 Lines are output while the 1 line input. HD/VD signal are also output doubled rate.
MS0319-E-03
47
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
QCIF (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b10
HD VD DVALID CLKO
(6.75MHz)
H H H
D[7:0]
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
32 clock @CLKO 65 clock @CLKO HD CLKO
(6.75MHz)
H In case of QCIF, there is a possibility that the Low period of CLKO signal just before the HV falling edge becomes 1.5 longer than usual case as left chart. Even in this case, falling edge of HV and falling edge of CLKO is same timing. H H H
HD VD DVALID CLKO
(6.75MHz)
D[7:0]
Cb 0
Y0
Cb 174
Y 174
Cr174
Y 175
0x80
0x80
352 clock @CLKO
12 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
48
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
Rotated QVGA (NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b10
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
58 clock @CLKO 198 clock @CLKO
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
Cb 0
Y0
Cb 119
Y 238
Cr119
Y 239
0x80
0x80
480 clock @CLKO
102 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
49
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
Rotated CIF(NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b10
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
58 clock @CLKO 150 clock @CLKO
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
Cb 0
Y0
Cb 143
Y 286
Cr143
Y 287
0x80
0x80
576 clock @CLKO
54 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
50
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
601output
(NTSC)
Register Set: VLF = 1'b0, OFORM[2:0] = 3'b110, OIF[1:0] = 2'b10
HD VD DVALID
(27.0MHz)
H H H
CLKO
D[7:0]
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 2
Y2
Cr2
Y3
Cb 4
Y4
128 clock @CLKO 244 clock @CLKO
27MHz
HD VD DVALID CLKO
(27.0MHz)
H H H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 716 Y 716 Cr716 Y 717 Cb 718 Y 718 Cr718 Y 719 0x80 0x10
0x80 0x10
1440 clock @CLKO
32 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
51
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart (HD/VD/DVALID mode)
QVGA (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b000, OIF[1:0] = 2'b10
HD VD DVALID
(12.2727MHz)
H H H
CLKO
D[7:0]
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 2
58 clock @CLKO 127 clock @CLKO
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
Cb 0
Y0
Cb 159
Y 318
Cr159
Y 319
0x80
0x80
640 clock @CLKO
13 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
52
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart
VGA (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b001, OIF[1:0] = 2'b10
HD VD DVALID CLKO
(24.5454MHz)
H H H
D[7:0]
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 1
Y2
Cr1
Y3
Cb 2
Y4
116 clock @CLKO 254 clock @CLKO
HD VD DVALID CLKO
(24.5454MHz)
H H H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 158 Y 636 Cr158 Y 637 Cb 159 Y 638 Cr159 Y 639 0x80 0x10
0x80 0x10
640 clock @CLKO
26 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
53
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart
CIF (PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b010, OIF[1:0] = 2'b10
HD VD DVALID
(13.5MHz)
H H H
CLKO
D[7:0]
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
64 clock @CLKO 140 clock @CLKO
HD VD DVALID CLKO
(13.5MHz)
H H H
D[7:0]
Cb 0
Y0
Cb 350
Y 350
Cr350
Y 351
0x80
0x80
704 clock @CLKO
20 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
54
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart
QCIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b011, OIF[1:0] = 2'b10
HD VD DVALID
(6.75MHz)
H H H
CLKO
D[7:0]
0x80
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
32 clock @CLKO 70 clock @CLKO HD CLKO
(6.75MHz)
H In case of QCIF, there is a possibility that the Low period of CLKO signal just before the HV falling edge becomes 1.5 longer than usual case as left chart. Even in this case, falling edge of HV and falling edge of CLKO is same timing. H H H
HD VD DVALID CLKO
(6.75MHz)
D[7:0]
Cb 0
Y0
Cb 87
Y 174
Cr87
Y 175
0x80
0x80
352 clock @CLKO
40 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
55
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart
Rotated QVGA (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b100, OIF[1:0] = 2'b10
HD VD DVALID
(12.2727MHz)
H H H
CLKO
D[7:0]
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
58 clock @CLKO 207 clock @CLKO
HD VD DVALID CLKO
(12.2727MHz)
H H H
D[7:0]
Cb 0
Y0
Cb 59
Y 118
Cr59
Y 119
0x80
0x80
240 clock @CLKO
93 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
56
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart
Rotated CIF (PAL)
Register Set : VLF = 1'b1, OFORM[2:0] = 3'b101, OIF[1:0] = 2'b10
HD VD DVALID
(13.5MHz)
H H H
CLKO
D[7:0]
0x10
0x80
0x10
Cb 0
Y0
Cr0
Y1
Cb 1
58 clock @CLKO 159 clock @CLKO
HD VD DVALID CLKO
(13.5MHz)
H H H
D[7:0]
Cb 0
Y0
Cb 143
Y 286
Cr143
Y 287
0x80
0x80
576 clock @CLKO
90 clock*@CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
57
2004 / 11
[ASAHI KASEI]
AK8855
Timing Chart
601output
(PAL)
Register Set: VLF = 1'b1, OFORM[2:0] = 3'b110, OIF[1:0] = 2'b10
HD VD DVALID
(27.0MHz)
H H H
CLKO
D[7:0]
0x80 0x10
0x80 0x10 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 1
Y2
Cr1
Y3
Cb 2
Y4
128 clock @CLKO 264 clock @CLKO
HD VD DVALID CLKO
(27.0MHz)
H H H
D[7:0] 0x80 0x10 Cb 0
Y0
Cr0
Y1
Cb 358 Y 716 Cr358 Y 717 Cb 359 Y 718 Cr359 Y 719 0x80 0x10
0x80 0x10
1440 clock @CLKO
24 clock* @CLKO
*This value is not guaranteed. Just reference value.
MS0319-E-03
58
2004 / 11
[ASAHI KASEI] AK8855 (3) 656 Interface Since synchronization with input by PLL is not made in 656 Interface mode, those specifications as [ 858 samples / Line, 525 Lines / Frame ] and [ 864 samples / Line, 625 Lines / Frame ] are not strictly satisfied which are specified by ITU-R BT.656. Picture data is defined based on HSYNC, and SAV is specified. In 656 Interface mode, HD / VD / DVALID signals are fixed to low. HD / VD signals can be output by register setting. Note )Relation between above mentioned various interface modes and their output format-related registers is summarized below. Related registers are [ OFORM1 : OFORM0 ]-bits and [ OIF2 : OIF0 ]-bits of Output Control 1 Register ( R/W ) [ Sub Address 0x01 ].
I/F mode [OIF1:OIF0]-bit 00 01 10 11 Camera I/F mode Camera I/F mode (with SAV/EAV) HD/VD/DVALID I/F Rec.656 [OFORM2:OFORM0]-bit 110(601output mode) O Not permited O O Except 110 set O O O Not permited
When items which are impossible to be set are selected, SAV / EAV codes are not guaranteed. By setting [ TRSVSEL ]-bit of Output Control 1 Register ( R/W ) [ Sub Address 0x01 ], it is possible to change V-bit shift point of the 656 specified Video Timing Reference code ( SAV / EAV ), separately from the above values. By properly setting [ TRSVSEL ]-bit, it is possible to make the shift point of V-bit compatible with ITU-R BT.656-3 or ITU-R BT.656-4 & SMPTE125M. Bit allocation of Output Control 1 Register is as follows. Sub Address 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 VDPSUP TRSVSEL OIF1 OIF0 LIMIT601 Default Value 0 0 0 0 0
bit 2 OFORM2 0
Default Value : 0x00 bit 1 bit 0 OFORM1 OFORM0 0 0
[ TRSVSEL ]-bit TRSVSEL-bit is a control bit to specify V-bit handling within Rec 656 EAV / SAV code. < V-bit value in Rec. 656 TRS signal and Line relation >
V-bit NTSC(525Lines) TRSVSEL=1 TRSVSEL=0 Based on ITU-R Based on ITU-R Bt.656-4 and Bt.656-3 SMPTE125M Line10 ~ Line263 Line20 ~ Line263 Line273 ~ Line525 Line283 ~ Line525 Line1 ~ Line9 Line264 ~ Line272 Line1 ~ Line19 Line264 ~ Line282 PAL(625Lines) TRSVSEL=0 TRSVSEL=1
V-bit = 0 V-bit = 1
Line23 ~ Line310 Line336 ~ Line623 Line1 ~ Line22 Line311 ~ Line335 Line624 ~ Line625
(4) About Field Signal Output The AK8855 has a Field signal output pin. Pin output and Field relation is shown as follows. FIELD Signal State field information Low Odd High Even Value of Field signal is determined during DVALID active. Field signal does not directly reflect input field , but it is a field signal which is forced to toggle at each VSYNC signal. Therefore, even when Odd Field only or Even Field only signal is input, Field signal also toggles.
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AK8855
Variable Frame Rate Function
The AK8855 can vary output Frame rate. Frame rate can be selected by [ FRMRT 1 : FRMRT 0 ]-bits of Control Register ( R/W ) [ Sub Address 0x04 ] as follows. NTSC : 30 / 15 / 7.5 [ fps ] PAL : 25 / 12.5 / 6.25 [ fps ] Output Timing is shown as follows. indicates " active ".
QVGA, CIF, QCIF, Rotated QVGA, Rotated CIF
Field DVALID(ODEV DVALID(ODEV DVALID(ODEV DVALID(ODEV DVALID(ODEV DVALID(ODEV
0,30fps) 1,30fps) 0,15fps) 1,15fps) 0,7.5fps) 1,7.5fps)
VGA,601
Field DVALID(30fps) DVALID(15fps) DVALID(7.5fps
Note 1 : Above diagrams are common for each of OFORM and OIF modes. Note 2 : when OIF[ 1:0 ] = 2'b 10 is set, VD / VAF are not output but it is output even during such Field ( Frame ) where HD / HV, DVALID are not output. Note 3 : in VGA, 601 mode, ODEV setting does not affect output. Note 4 : when Vertical Sync is disturbed during switching signals etc., above timing may not temporarily be satisfied.
Digital Pixel Interpolator
This function is equipped to align pixel position in vertical direction.
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AK8855
Notification Function of Internal Conditions
The AK8855 has Status Register ( R/W ) [ Sub Address 0x10 ] to notify externally the AK8855 internal condition. Bit allocation of Status Register is as follows. Sub Address 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VBWSSDE EXTDET CCDET AGCSTS CPLLLCK PKWHITE COLKILST NSIG T (1) No Signal Decision The AK8855 makes a decision of no signal input condition. When it is decided to be no input signal, data output becomes Black level output ( Y = 0x10, Cr / Cb = 0x80 ). Its result is notified to outside by output pin NSIG and [ NSIG ]-bit of Status Register. Output Logical State is as follows. Signal condition [NOSIG]-bit NSIG pin With signal input 0 0 No signal input 1 1 (2) COLKILST This is to indicate that Color Killer Function has been activated as Color signal level is very small. [COLKIL]-bit Input level Condition 0 Normal signal 1 Color Killer is enabled (3) Input Level Overflow Notification Function This function is activated when the decoded result of Luminance signal exceeds 255. [ PKWHITE ]-bit "1" is set to this bit when an overflow of Luminance signal is detected. When [ PKWHITE ]-bit becomes "1", an overflow occurred at Luminance signal processing path. [PKWHITE]- bit Input level Condition 0 Input signal overflow occurred 1 No input overflow occurred (4) Color PLL Status This is to indicate PLL Lock condition with input Color Burst signal. [ CPLLLCK ]-bit [CPLLLCK]-bit Input level 0 It is locked with input Color Burst signal 1 It is not locked with input Color Burst signal (5) AGC Status This is to indicate status of adaptive AGC [ AGCSTS ]-bit [AGCSTS]-bit Input level 0 Operation in Sync AGC 1 Operation in Peak AGC
Condition
Condition
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AK8855
At No Input Signal Condition
Two output modes can be selected when no Video signal is input to the AK8855. Default value is Black code output. Setting is made by NSIGMD-bit of Output Control 2 Register ( R/W ) [ Sub Address 0x02 ]. Detection of no signal condition is notified by a hardware pin and Status Register ( R / W ) [ Sub Address 0x10 ]. [ NSIGMD ]-bit This is a control bit to set output signal processing when no signal is input. [NSIGMD]-bit Output signal when no signal is input 0 1 Black code output Input signal is directly output as is.
Condition Y = 0x10 Cb/Cr = 0x80 So-called " Sand-Storm " mode output.
Power-Down Mode
The AK8855 has a power-saving wait mode function. PDN pin is used to put the AK8855 into power-saving mode, including digital block. By setting this pin to low, all blocks in Analog and Digital parts are put into power-saving mode. Recover from the power-saving mode by PDN pin , a Reset sequence must be executed. When to turn down power supplies except for PVDD, a power-down sequence must be followed, using PDN pin and then turn-down AVDD /DVDD after power-down condition is established. It is recommended to fix the digital output pins to PVDD power supply or to set OE pin = high ( high output ).
Output Pin Condition
Output pins of the AK8855 are controlled by OE ( Output Enable ) pin and RSTN pin conditions. Output pin conditions are : After Reset sequence After Power RSTN = Low up PDN = Low PDN = High OE = High unknown Hi-z High Data output OE = Low Hi-z Hi-z Hi-z Hi-z Note ) there is a possibility that leak current may flow at OE = Low ( Hi-Z condition ). It is recommended that output pins are set to same PVDD potential or OE pin is set to High in Power-Down mode setting. Pins to be controlled by OE pin are, CLKO, D [ 7 : 0 ], FIELD, HD / HV, VD / VAF, NSIG and DVALID pins.
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AK8855
Device Control Interface
The AK8855 is controlled via I2C Bus Control Interface. [ I2C SLAVE Address ] I2C Slave Address is 0x88 [ I2C Control Sequence ] (1) Write Sequence When the Slave Address of the AK8855 Write mode is received at the first byte, Sub Address at the second byte and Data at the third and succeeding bytes are received. There are 2 operations in Write Sequence - a sequence to write at every single byte, and a sequential write operation to write multiple bytes successively. (a) 1 Byte Write Sequence
S lave Address w 8-bits A 1bit
Sub Address 8-bits
A 1bit
Data 8-bits
A 1bit
Stp
(b) Multiple Bytes ( m-bytes ) Write Sequence ( Sequential Write Operation )
S Slave Address 8-bits w A 1bit
Sub Address(n) 8-bits
A 1bit
Data(n) 8-bits
A 1bit
Data(n+1) 8-bits
A 1bit
---
Data(n+m) 8-bits
A 1bit
stp
(2) Read Sequence When the Slave Address of the AK8855 Read mode is received, Data at the second and succeeding bytes are transmitted.
S Slave Address 8-bits
w A
Sub Address(n) 8-bits
A
rS
Slave Address 8-bits
R
A
Data1 8-bits
A
Data1 8-bits
A
Data2 8-bits
A
---
Data n 8-bits
stp
1
1
1
1
1
1
1
Note ) At Sequential Read Operation, the first byte Read-out Data is repeatedly output ( this does not happen in a normal, single byte Read operation ). Abbreviated terms listed above mean : S, rS A Astp R/W : Start Condition : Acknowledge ( SDA Low ) : Not Acknowledge ( SDA High ) : Stop Condition 1 : Read 0 : Write : to be controlled by the Master Device. Micro-computer interface is output normally . : to be controlled by the Slave Device. To be output by the AK8855.
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AK8855
Register Definition
Sub Address 0x00 0x01 0x02 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Register Input Video standard Register Output Control 1 Register Output Control 2 Register Control Register PGA Control Register Contrast Control Register Brightness Control Register Saturation Control Register HUE Control Register Request VBI Info Register Status Register Macrovision Status Register Closed Caption 1 Register Closed Caption 2 Register Extended Data 1 Register Extended Data 2 Register VBID/WSS 1 Register VBID/WSS 2 Register Device & Revision ID Register Default 0x00 0x00 0x00 0x00 0x46 0x80 0x00 0x80 0x00 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R R R R R R R R Function To set the Input signal Standard To set output picture sizes etc To set output characteristics of output pins Various control registers. PGA Control Register Contrast Control Register Brightness Control Register Saturation Control Register HUE Control Register Request VBI Info Register Status Register Macrovision Status Register Closed Caption Data 1 register Closed Caption Data 2 register. Closed Caption Extended Data 1 register. Closed Caption Extended Data 2 register. VBID ( CGMS-A ) / WSS1 Data register VBID ( CGMS-A ) / WSS 2 Data register Device & Revision ID Register
0x37
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[ASAHI KASEI] Input Video Standard Register (R/W) [Sub Address 0x00] Register to set input signal Sub Address 0x00 bit 7 bit 6 Reserved Reserved 0 0
AK8855
bit 5 Reserved 0
bit 4 bit 3 AINSEL VLF Default Value 0 0
bit 2 VCEN 0
Default Value : 0x00 bit 1 bit 0 VSCF1 VSCF0 0 0
Input Video Standard Register Definition Register BIT Name bit 0 ~ bit 1 VSCF0 ~ VSCF1
R/ W
Definition to set Sub-carrier frequency of input video signal VSCF1 - VSCF0 [MHz] 00 : 3.57954545 01 : 3.57561188 10 : 3.5820558 11 : 4.43361875 to set Color Encoding System of input video signal. 0: NTSC 1: PAL to set Line Frequency of input video signal. 0 : 525 Lines 1 : 625 Lines to select AIN Input Select switch. 0: to decode AIN 1 1: to decode AIN 2 Reserved
Sub carrier Frequency
R/ W
bit 2
VCEN
Video Color Encode
R/ W R/ W R/ W R/ W
bit 3
VLF
Video Line Frequency
bit 4 bit 5 ~ bit 7
AINSEL
AIN Select bit
Reserved
Reserved
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[ASAHI KASEI] Output Control 1 Register (R/W) [Sub Address 0x01] Register to set the output data format. Sub Address 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 VDPSUP TRSVSEL OIF1 OIF0 LIMIT601 Default Value 0 0 0 0 0 Output Control 1 Register Definition Register BIT Name
AK8855
bit 2 OFORM2 0
Default Value : 0x00 bit 1 bit 0 OFORM1 OFORM0 0 0
R/ W
Definition to set output picture sizes. 000: QVGA 001: VGA ( interlaced output ) 010: CIF 011: QCIF 100: rotated QVGA ( 240 X 180 ) 101: rotated CIF ( 288 X 216 ) 110: 601 output 111: Reserved to set Min. / Max. of output data. 0 : 1 - 254 (Y / Cb / Cr) 1 : 16 - 235 (Y) / 16 - 240 ( Cb / Cr ) when "1" is set at LIMIT601 register, data smaller than 16 is clipped to 16 and data larger than 235 / 240 ( Y / Cb, Cr ) is clipped to 240. to set output interface mode. 00: Camera Interface mode ( without SAV / EAV ) 01: Camera Interface mode ( with SAV / EAV ) 10: HD / VD mode 11: 656 Interface mode In setting modes of 01 / 11, HD / VD output is fixed to low. to switch shift line of V-bit of EAV / ASAV which is included in TRS. This register is valid when OFORM [ 2:0 ] = 110. NTSC system ( at 525 Line input ) TRSVSEL=0 : V = 1 when Line 1 ~ Line 9 / Line 264 ~ Line 272 V = 0 when Line 10 ~ Line 263 / Line 272 ~ Line 525 TRSVSEL=1: V = 1 when Line 1 ~ Line 19 / Line 264 ~ Line 282 V = 0 when Line 20 ~ Line 263 / Line 283 ~ Line 525 PAL system ( at 625 Line input ) Regardless of set value of TRSVSEL-bit, V = 1 when Line 1 ~ Line 22 / Line 311 ~ Line 355 / Line 624 ~ Line 625 V = 0 when Line 23 ~ Line 310 / Line 336 ~ Line 623 When Frame Rate Variable Function is activated in HD / VD mode and 656 I / F mode, 0 : VD / VAF pulse is not output at the Frames which are not active. 1 : VD / VAF pulse is output even at the Frames which are not active.
bit 0 ~ bit 2
OFORM1 ~ OFORM2
Output Format Set bit
R/ W
bit 3
LIMIT601
601 Output Limit
R/ W
bit 4 ~ bit 5
OIF0 ~ OIF1
Output interface set bit
R/ W
bit 6
TRSVSEL
Time Reference Signal V Select bit
R/ W
bit 7
VDPSUP
VD Pulse SUPress
R/ W
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[ASAHI KASEI] Output Control 2 Register (R/W) [Sub Address 0x02] Register to set polarity of output pin and to set output condition when no input signal is fed. Sub Address 0x02 bit 7 bit 6 OF_OFF NSIGMD 0 0 bit 5 DVALACT 0 bit 4 bit 3 HVACT CLKINV Default Value 0 0 bit 2 DVALIDP 0
AK8855
Default Value: 0x00 bit 1 bit 0 VDP HDP 0 0
Output Control 2 Register Definition Register BIT Name bit 0 HDP HD pin Polarity set bit
R/ W R/ W R/ W R/ W R/ W
Definition to set polarity of HD signal. 0: Active Low 1: Active High to set polarity of VD signal. 0: Active Low 1: Active High to set polarity of DVALID signal. 0: Active Low 1: Active High to set polarity of CLKO. 0: normal output ( data should be taken at the rising edge ) 1: phase relation between data and clock is inverted ( data should be taken at the falling edge ). to output HD & VD in EAV / SAV Interface mode. no output ( fixed to low ) 1 : to output to output DVALID signal in EAV / SAV Interface mode. 0: no output ( fixed to low ) 1: to output to decide output condition when no signal input condition is detected. 0 : to output Black level 1 : to output input condition directly as is ( " Sand-Storm " condition ). to turn off the vertical interpolator filter in the rotated QVGA output operation. 0 : with vertical interpolator filter 1 : without vertical interpolator filter
bit 1
VDP
VD pin Polarity set bit DVALID pin Polarity set bit
bit 2
DVALDP
bit 3
CLKINV
CLK invert set bit
bit 4
HVACT
HD/VD action bit
R/ W
bit 5
DVALACT
DVALID action bit
R/ W
bit 6
NSIGMD
No SiGnal Output MoDe
R/ W
bit 7
OF_OFF
OutputFilter_OFF bit
R/ W
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[ASAHI KASEI] Reserved Register (R/W) [Sub Address 0x03] Sub Address 0x03 bit 7 bit 6 Reserved Reserved 0 0 bit 5 Reserved 0 bit 4 bit 3 Reserved Reserved Default Value 0 0 bit 2 Reserved 0
AK8855
Default Value: 0x00 bit 1 bit 0 Reserved Reserved 0 0
Reserved Register Definition Register BIT Name bit 0 ~ Reserved Reserved Register bit 7
R/ W R/ W Reserved
Definition
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[ASAHI KASEI] Control Register (R/W) [Sub Address 0x04] Control Register Sub Address 0x04 bit 7 bit 6 CNTSEL DTFIX 0 0 bit 5 ODEV 0 bit 4 bit 3 FRMRT1 FRMRT0 Default Value 0 0 bit 2 COLKIL 0
AK8855
Default Value: 0x00 bit 1 bit 0 ACC AGC 0 0
Control Register Definition Register BIT Name bit 0 bit 1 bit 2 AGC ACC COLKIL AGC set bit ACC set bit Color Killer Set bit
R/ W R/ W R/ W R/ W
Definition 0 : AGC disabled ( PGA manual setting is possible ) 1 : AGC enabled 0 : ACC Disable 1 : ACC Enable 0 : Color Killer enabled 1 : Color Killer disabled to set Frame Rate [ Frame / sec ] FRMRT 1:0 ( 525 / 625 ) 00: 30/25 01: 15/12.5 10: 7.5/6.25 11: Reserved to set decode field when QVGA / CIF / QCIF decodings are made. 0 : to decode Odd Field 1 : to decode Even Field to fix data in the data path while data is not output. 0 : OFF 1 : ON ( data in the Data path is fixed ) to set the start point of Contrast adjustment 00 : Contrast varies, starting at Luminance level of 128 ( gray ) as a center value. 1 : Contrast varies, starting at Luminance level of 16 ( black ) as a center value.
bit 3 ~ bit 4
FRMRT0 ~ FRMRT1
Frame Rate Set bit
R/ W
bit 5
ODEV
ODD Even Select bit
R/ W
bit 6
DTFIX
DaTa Fix control bit
R/ W
bit 7
CNTSEL
Contrast mode select bit
R/ W
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[ASAHI KASEI] PGA Control Register (R/W) [Sub Address 0x05] Register to set gain of PGA. When AGC function is enabled, gain value set by AGC is set to this register. Sub Address 0x05 bit 7 bit 6 Reserved PGA6 0 1 bit 5 PGA5 0 bit 4 bit 3 PGA4 PGA3 Default Value 0 0 bit 2 PGA2 1
AK8855
Default Value: 0x46 bit 1 bit 0 PGA1 PGA0 1 0
PGA Control Register Definition Register BIT Name bit 0 PGA0 ~ ~ PGA Gain Set bit 6 PGA6 bit 7 Reserved Reserved
R/ W R/ W R/ W
Definition to set gain of PGA. PGA can be adjusted in approximately 0.1 dB / step. Reserved
Note ) when to read this register while AGC is enabled, the PGA value which is set by AGC is returned. It is possible to write value by user ( user-set-value ) while AGC is enabled, but its value is not written to PGA. A returned value made by register read operation also becomes above mentioned AGC set-value. When AGC is disabled, user-set-value is valid, and its value ( user-set-value ) is returned by Register Read operation.
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[ASAHI KASEI] Contrast Control Register (R/W) [Sub Address 0x06] Register to make Contrast Adjustment. Default value 0x80 corresponds to un-adjusted value. Sub Address 0x06 bit 7 bit 6 CONT7 CONT6 1 0 bit 5 CONT5 0 bit 4 bit 3 CONT4 CONT3 Default Value 0 0 bit 2 CONT2 0
AK8855
Default Value: 0x80 bit 1 bit 0 CONT1 CONT0 0 0
Contrast Control Register Definition Register BIT Name bit 0 ~ bit 7 CONT0 ~ CONT7 Contrast Control
R/ W R/ W
Definition to make Contrast Adjustment. Setting can be made in 1 / 256 step and setting range is from 0 to 255 / 128. Default value is 0x80.
Brightness Control Register (R/W) [Sub Address 0x07] Register to make Brightness Adjustment. Default value 0x00 corresponds to un-adjusted value. Sub Address 0x07 bit 7 bit 6 BR7 BR6 0 0 bit 5 BR5 0 bit 4 bit 3 BR4 BR3 Default Value 0 0 bit 2 BR2 0 Default Value: 0x00 bit 1 bit 0 BR1 BR0 0 0
Brightness Control Register Definition Register BIT Name bit 0 BR0 ~ ~ Brightness Control bit 7 BR7
R/ W R/ W
Definition to make Brightness Adjustment. Setting is made in 2's complement number.
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[ASAHI KASEI] Saturation Control Register (R/W) [Sub Address 0x08] Register to make Color Saturation Adjustment. Default value corresponds to un-adjusted value. Sub Address 0x08 bit 7 bit 6 SAT7 SAT6 1 0 bit 5 SAT5 0 bit 4 bit 3 SAT4 SAT3 Default Value 0 0 bit 2 SAT2 0
AK8855
Default Value: 0x80 bit 1 bit 0 SAT1 SAT0 0 0
Saturation Control Register Definition Register BIT Name bit 0 ~ bit 7 SAT0 ~ SAT7
R/ W
Definition to make Saturation Adjustment. Setting value can be made in 1 / 256 step and setting range is from 0 to 255 / 128. SAT7:SAT0 0 : 0 x ( no color exists ) 0xff : 255 / 128 x
Saturation Control
R/ W
HUE Control Register (R/W) [Sub Address 0x09] Register to make Hue Adjustment. Default value 0x00 corresponds to un-adjusted value. Sub Address 0x09 bit 7 bit 6 HUE7 HUE6 0 0 bit 5 HUE5 0 bit 4 bit 3 HUE4 HUE3 Default Value 0 0 bit 2 HUE2 0 Default Value: 0x00 bit 1 bit 0 HUE1 HUE0 0 0
HUE Control Register Definition Register BIT Name bit 0 ~ bit 7
R/ W
Definition to make Hue adjustment. Setting should be made in 2's complement number. Default value is 0x00. Setting is made in 1 / 256 step ( approximately 0.35 degree step ), which ranges +/- 45 degrees.
HUE0 ~ HUE7
HUE Control
R/ W
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[ASAHI KASEI] AK8855 Request VBI Info Register (W) [Sub Address 0x0A] Register to request decoding of VBLANK information such as Closed Caption Data / Extended Data / VBID ( CGMS ) / WSS Data etc. When "1" is written to the decode request bit of each VBLANK information, the AK8855 is put into Data Decode Ready state and waits for Data. After decoding is completed, "1" is written to CCDET-bit / EXTDET-bit / VBWSSDET-bit which correspond to a Status Register ( R / W ) [ Sub Address 0x10] Request, and decoded data are written to Closed Caption Data 1 / 2 Registers, Extended Data 1 / 2 Registers and VBID / WSS Data 1/ 2 Registers respectively. Sub Address 0x0A bit 7 bit 6 Reserved Reserved 0 0 Default Value: 0x00 bit 1 bit 0 EXTRQ CCRQ 0 0
bit 5 Reserved 0
bit 4 bit 3 Reserved Reserved Default Value 0 0
bit 2 VBWSRQ 0
Request VBI Info Register Definition Register BIT Name bit 0 CCRQ
R/ W
Definition to request decoding of Closed Caption Data 0:1 : decode request to request decoding of Extended Data 0:1 : decode request to request decoding of VBID / WSS Data 0:1 : decode request Reserved
Closed Caption Data Decode W Request Extended Request Data Decode W
bit 1
EXTRQ
bit 2 bit 3 ~ bit 7
VBWSRQ
VBID Data Decode Request
W
Reserved
Reserved
W
Note ) when "1" is written to RQ-bit, CCDET-bit / EXTDET-bit / VBWSSDET-bit are cleared to "0" which correspond to a Status Register Request.
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[ASAHI KASEI] Status Register (R/W) [Sub Address 0x10] Register to indicate internal conditions of the AK8855. Sub Address 0x10
bit 7 VBWSSDET bit 6 EXTDET bit 5 CCDET bit 4 AGCSTS bit 3 CPLLLCK bit 2 PKWHITE bit 1 COLKILST
AK8855
bit 0 NSIG
Status Register Definition Register BIT Name bit 0 NOSIG No Signal
R/ W R
Definition to judge existence / non-existence of input signal. 0 : signal is being input 1 : no signal input condition to judge if Color Killer is active or not. 0 : Color Killer is in-active 1 : Color Killer process is active to detect if AD-converted input signal is over-flowing or not. 0 : normal 1 : input level is over-flowing to show Lock condition of Color PLL 0 : PLL is locked 1 : PLL is not locked 0 : Sync AGC operation 1 : Peak AGC operation to show that decoded data exist at Closed Caption Data 1 / 2 registers. 0 : no Closed Caption Data exists 1 : decoded Closed Caption Data exists to show that decoded data exist at Extended Data 1 / 2 Registers 0 : no Extended Data exists 1 : decoded Extended Data exists to show that decoded data exist at VBID / WSS Data 1 / 2 Registers. 0 : no VBID / WSS data exists 1 : decoded VBID / WSS data exists
bit 1
COLKILST
Color killer
R
bit 2
PKWHITE
Peak White Detection
R
bit 3 bit 4
CPLLLCK AGCSTS
Color PLL Locked Flag AGC Status bit
R R
bit 5
CCDET
Closed Caption Detect
R
bit 6
EXTDET
Extended Data Detect
R
bit 7
VBWSDET
VBID / WSS Data Detect
R
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[ASAHI KASEI] Macrovision Status Register (R/W) [Sub Address 0x11] Register to indicate the Macrovision Detect Result. Sub Address 0x11 bit 7 bit 6 Reserved PSPDET bit 5 AGCPDET bit 4 BPPDET bit 3 SYNCRED bit 2 CSTYPE bit 1 CSDET
AK8855
bit 0 AGCDET
Macrovision Status Register Definition Register BIT Name bit 0 AGCDET AGC Process Detect
R/ W R
Definition to show that Macrovision AGC Process is included on input signal. 0 : no Macrovision AGC Process is detected 1 : Macrovision AGC Process is detected to show that Macrovision Color Stripe Process is included on input signal. 0 : no Color Stripe process 1 : Color Stripe process is detected to show types of Color Stripe which is included on input signal 0 : Color Stripe Type 2 1 : Color Stripe Type 3 to show that Sync Reduction is detected 0:1 : Sync Reduction is detected to show that end of Field Back Porch Pulse is detected 0:1 : end of Field Back Porch Pulse is detected to show that AGC Pulse is detected. 0:1 : AGC Pulse is detected to show that Pseudo Sync Pulse is detected. 0:1 : Pseudo Sync Pulse is detected Reserved
bit 1
CSDET
Color Stripe Detect
R
bit 2
CSTYPE
Color Stripe Type
R
bit 3
SYNCRED
Sync Reduction bit
R
bit 4
BPPDET
Back Porch Pulse Detect bit
R
bit 5
AGCPDET
AGC Pulse Detect bit Pseudo Sync Pulse Detect bit Reserved bit
R
bit 6 bit 7
PSPDET Reserved
R R
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[ASAHI KASEI] Closed Caption 1 Register (R) [Sub Address 0x12] Register to store Closed Caption Data. Sub Address 0x12 bit 7 bit 6 bit 5 bit 4 CC7 CC6 CC5 CC4
AK8855
bit 3 CC3
bit 2 CC2
bit 1 CC1
bit 0 CC0
Closed Caption 2 Register (R) [Sub Address 0x13] Register to store Closed Caption Data. Sub Address 0x13 bit 7 bit 6 bit 5 bit 4 bit 3 CC15 CC14 CC13 CC12 CC11 Extended Data 1 Register (R) [Sub Address 0x14] Register to store Closed Caption Extended Data. Sub Address 0x14 bit 7 bit 6 bit 5 bit 4 EXT7 EXT6 EXT5 EXT4
bit 2 CC10
bit 1 CC9
bit 0 CC8
bit 3 EXT3
bit 2 EXT2
bit 1 EXT1
bit 0 EXT0
Extended Data 2 Register (R) [Sub Address 0x15] Register to store Closed Caption Extended Data. Sub Address 0x15 bit 7 bit 6 bit 5 bit 4 bit 3 EXT15 EXT14 EXT13 EXT12 EXT11
bit 2 EXT10
bit 1 EXT9
bit 0 EXT8
VBID/WSS 1 Register (R) [Sub Address 0x16] Register to store VBID data and to store WSS data. Sub Address 0x16 bit 7 bit 6 bit 5 bit 4 Reserved Reserved VBID1 VBID2 Reserved Reserved G4-13 G4-12 VBID/WSS 2 Register (R) [Sub Address 0x17] Register to store VBID data and to store WSS data. Sub Address 0x17 bit 7 bit 6 bit 5 bit 4 VBID7 VBID8 VBID9 VBID10 G2-7 G2-6 G2-5 G2-4
bit 3 VBID3 G4-11
bit 2 VBID4 G3-10
bit 1 VBID5 G3-9
bit 0 VBID6 G3-8
bit 3 VBID11 G1-3
bit 2 VBID12 G1-2
bit 1 VBID13 G1-1
bit 0 VBID14 G1-0
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[ASAHI KASEI] Device & Revision ID Register (R) [Sub Address 0x18] Register to show Device ID & Revision of the AK8855. Device ID of the AK8855 is 55 in decimal. Initial Version of the Revision ID is 0x00. Revision number is modified only when a control software needs to be modified. Sub Address 0x18 bit 7 bit 6 REV1 REV0 0 0
Revision Register Definition
AK8855
bit 5 DID5 1
bit 4 DID4 1
bit 3 DID3 0 R/ W
bit 2 DID2 1
Default Value 0x37 bit 1 bit 0 DID1 DID0 1 1
BIT bit 0 ~ bit 3 bit 4 ~ bit 7
Register Name DID0 ~ DID5 REV0 ~ REV1
Definition to show Device ID Device ID is 55 ( decimal ) ( 0x37h ). to show Revision information REV1 - REV0 Initial version is 0x00
Revision bit
R
Device ID
R
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AK8855
System Connection Example
Micro Processor 2 (I C Controller)
PVDD (1.8V or 3.0V) Video IN SDA
39 0.1u
SCL RSTN PDN
OE PVDD PVSS
AIN1 AIN2
39
IREF VRP VCOM VRN 4.7k
0.1u 0.1u 0.1u
D[7..0] NSIG CLKO DVALID HD/HV VD/VAF FIELD TEST0 TEST1
AK8855
CLKMOD
XTI 24.5454MHz XTO 18pF 22pF
TEST2
Analog 3.0V
Digital 3.0V AVDD AVSS DVSS DVDD
10uF
0.1uF
0.1uF
10uF
Analog GND
Digital GND
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AK8855
Package Drawing
0.05 M S AB
9876 54 3 21 A B C D E F G H J
A
5.0 0.1
57 - 0.3 0.05
B
5.0 0.1
4.0 0.5
0.5
S
MS0319-E-03
0.25 0.05
0.89 0.1
0.08 S
79
2004 / 11
[ASAHI KASEI]
AK8855
Package Marking Drawing
8855 XXXX
a. Package type : BGA b. Number of pins : 57 pins ( including an index pin ) c. Product number : 8855 d. Control Code : xxxxx ( 5 digit number )
MS0319-E-03
80
2004 / 11
[ASAHI KASEI]
AK8855
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0319-E-03
81
2004 / 11

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